[USRP-users] Ettus UBX-160 vs SBX-120

Martin Braun martin.braun at ettus.com
Wed Jul 5 15:02:37 EDT 2017


We do have DDCs on the FPGA though. Can you run at 100 MHz?

-- M

On 07/04/2017 01:36 AM, Marcus Müller via USRP-users wrote:
> Exactly!
> 
> So, if your ADC runs at 120 MHz, the unambiguously representable
> baseband is -60 MHz to +60MHz.
> 
> Now you have a baseband signal at +65 MHz that (barely, but still)
> passes through the analog anti-aliasing filter, what happens?
> 
> Exactly, it shows up at -55 MHz. If you had useful signal at -55 MHz,
> bad luck, it's now superimposed with the alias of the 65 MHz signal.
> 
> Effectively, that means that if you use an anti-aliasing filter with a
> passband that is exactly as wide as the Nyquist bandwidth of the ADC
> you're dealing with, you can't really use the upper and lower part of
> the observed spectrum, because that is overlayed with the lower and
> upper transition width of the filter, respectively.
> 
> "Can't use", "Passband", "Transition Width" are all relative to what
> distortions you're able to accept, by the way.
> 
> Best regards,
> 
> Marcus
> 
> 
> On 07/04/2017 10:26 AM, Simon Olvhammar via USRP-users wrote:
>> Thank you Keyong Su Shin,
>>
>> However I suppose you mean aliasing just at the band edges?
>> I get around 100 MHz of good data when using 120 MS/s on the SBX-120
>> daughterboard.
>>
>> Regards
>> Simon
>>
>> On Mon, Jul 3, 2017 at 3:18 PM, Kyeong Su Shin <ksshin at uw.edu
>> <mailto:ksshin at uw.edu>> wrote:
>>
>>     Hello Simon Olvhammar:
>>
>>     Just one more note:
>>
>>     A relevant e-mail thread achieve, since you are apparently using
>>     ADC sampling rate of 120MS/s on SBX-120 daughterboards:
>>
>>     http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-February/018075.html
>>     <http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-February/018075.html>
>>
>>     To get better data quality, you may want to sample faster and then
>>     do digital filtering -> decimation (USRP will do that for you, if
>>     you are fine with integer decimators). This may prevent you from
>>     using the 120MHz bandwidth, but improve the overall data quality.
>>
>>     Regards,
>>     Kyeong Su Shin
>>
>>     On Mon, Jul 3, 2017 at 1:35 AM, Simon Olvhammar via USRP-users
>>     <usrp-users at lists.ettus.com <mailto:usrp-users at lists.ettus.com>>
>>     wrote:
>>
>>         Hi,
>>
>>         I am not sure if I understand correctly.
>>         How are the ADC to slow if I use a master clock rate of 120
>>         MHz and sampling rate of 120 MHz on a UBX-160? I don't need
>>         160 MHz bandwidth only 120 MHz.
>>
>>         Regards
>>         Simon
>>
>>         On 06/28/2017 04:12 PM, Sylvain Munaut wrote:
>>
>>             Hi,
>>
>>
>>                 We currently running a system with a Ettus x310 and a
>>                 SBX-120.
>>                 We also a have UBX-160 daughter board.
>>
>>                 For several reasons, mainly due to computer
>>                 performance limitations, we can
>>                 only run with a complex sampling rate of 120 MHz.
>>                 My question is if I will see any improvement in
>>                 performance, e.g. filter
>>                 characteristics, if I instead use the UBX-160 and run
>>                 it at 120 MHz compared
>>                 to SBX-120 at 120 MHz or are they similar?
>>
>>             You can't do that.
>>
>>             If you have the master clock-rate at 120 MHz and use a 160
>>             MHz wide
>>             daugtherboard, you will get aliasing because the ADC are
>>             too slow.
>>             You'd have to go to a 100 MHz samplerate for it to work.
>>             (200 MHz
>>             sampled by the ADC then HW decimated by 2 to 100 Msps).
>>
>>             Cheers,
>>
>>                 Sylvain
>>
>>
>>
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>>
>>
>>
>>
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> 
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