[USRP-users] Two questions on X310 at 200MSps RX

Derek Kozel derek.kozel at ettus.com
Mon Jul 3 12:27:10 EDT 2017

Hello Leo,

The DMA FIFO is not used on the receive side in the default X310
configuration. The "large" buffers in this case are on the receiving host
computer's NIC and in UHD. Strictly speaking it is not the Ethernet latency
which is the problem, it is the variability of the latency. The radio has a
hard requirement of receiving N samples per second and the Ethernet
connection is only supplying N per second on average. The DRAM FIFO absorbs
the variability.

It does not matter if you are not transmitting or not, given fast enough
host hardware and some appropriate tuning of your OS' network stack it is
possible to receive two streams of 200 MS/s (or four of 100 MS/s in the
TwinRX case).


On Mon, Jul 3, 2017 at 2:53 PM, Leandro Echevarría via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hello all,
> I'm working on a system where the transmitted samples are provided by the
> FPGA, and not by the host (actually, they're loaded on DRAM in an
> initializing step). And I've got two questions about this approach:
> 1. We're planning on dropping the DMA FIFO block entirely, to gain
> exclusive access to the DRAM controller. I've read here [1] that the DMA
> FIFO is necessary when transmitting using samples coming from the host, due
> to Ethernet latency. But is this also true for receiving? Should I be able
> to stream samples @ 200 MSps from the radio core to the host without using
> a DMA FIFO in the middle?
> 2. We're using two 10 Gbps SFP+ Ethernet cables to connect the board to
> the host. Given we will not transmit out of the host, is it safe to say
> we'll be able to receive two 200 MSps streams from two daughterboards, one
> through each Ethernet connection?
> Thanks a lot!
> Leo
> [1] https://kb.ettus.com/RFNoC#When_do_I_use_an_RFNoC_FIFO_
> in_my_flowgraph_and_which_kind_if_any.3F
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