[USRP-users] rx data structure of E310

Marcus Müller marcus.mueller at ettus.com
Thu Mar 31 11:28:44 EDT 2016


Dear wwd,

thank you for the descripton of your system! That is very helpful in
understanding how to be of assistance.

On 31.03.2016 16:52, wwd wrote:
> For the first step, what I am trying to do is a very simple test
> implementation.
>
> I use a signal waveform generator to generate a sinus signal, then let
> it pass through E310 and save the samples to SD card. Finally, I try
> to plot the samples to verify all the configurations in E310 are corrects.
>
> So what I have done is:
>
> 1.
>     Image Freq=80MHz, Vp-p=60mV
> 2.
>     Image
>
> The center frequency=79.999MHz, I suppose I will get 1KHz after LO; 
10 MHz is a very high sampling rate for the E310, and usually the SD
card controller can not write that fast.

> the sample rate=10MHz; Master_clock_rate=60MHz; and I use this type of
> SD card
> Image
> The UHD and FPGA, I am using the newest RFNOC version:uhd-rfnoc-radio-redo
> Therefore, I have some warning of overrun, but it doesn't have serious
> problem for my results.
I'd still recommend using a lower rate; there's no use in having 10 MS/s
if your signal is limited to a little more than 1kHz!

Notice that you'd see the sine at exactly 1kHz if the oscillator of your
signal generator and the E310 were perfectly in sync. In general, they
are not!
>
>  3. In MATLAB, I separate each 16bits data one for Q and one for I.
>     Then I pull out the higher 12bits, because I think they are real
>     data after ADC and do the two's complement to transfer it to
>     signed int.
>
As said, no, you should definitely use all 16 bits!
Your ADC is in fact only a 12 bit ADC, but it runs at your master clock
rate of 60 MHz, so you get an oversampling of 6! That is an advantage in
SNR and in bit width, because the DSP chain uses good filters to reduce
the 60MS/s to 10MS/s, widening the bit width of the samples in the process.
>
>  3. So finally I have two figures of sample data, one for I and the
>     other is Q:
>
>  
> Image
>
>
>
>
>
>
>
>
>
>
>
>
> But they don't have the same amplitude, and don't have the different
> on phase. So I want to know what's the problem could be, am I missing
> something.
You really can't trust any data that was generated with overflows.
Reduce the sampling rate, don't throw away bits, and please verify the
problem persists.
> And I have another silly question is the master_clock_rate is the
> frequency applied on ADC and sample rate is between usrp and host pc, 
exactly
> in E310 is between FPGA and ARM cpu, 
> or it is the final frequency after the decimating filters after ADC?
sampling rate = what you get in Software = output of decimating filters
in DSP chain in Hardware/FPGA.
master clock rate = rate of ADC

Best regards,
Marcus
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