[USRP-users] rx data structure of E310

wwd wwd_usrp at hotmail.com
Wed Mar 30 09:45:07 EDT 2016


Dear Marcus,

I have a basic question about the data structure in FPGA and UHD.

When I looked at the FPGA source code, I found these codes:

//------------------------------------------------------------------
   // CODEC capture/gen
//------------------------------------------------------------------
   wire mimo;
   wire codec_arst;
   wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1, tx_i0, tx_q0, tx_i1, tx_q1;
   wire [31:0] rx_data0, rx_data1, tx_data0, tx_data1;
*assign rx_data0      = {rx_i0,4'd0,rx_q0,4'd0};**
**  assign rx_data1      = {rx_i1,4'd0,rx_q1,4'd0};*
   assign {tx_i0,tx_q0} = {tx_data0[31:20],tx_data0[15:4]};
   assign {tx_i1,tx_q1} = {tx_data1[31:20],tx_data1[15:4]};


I want to make sure if in the UHD side, the rx data keeps the same 
structure. And the data samples are carried in two's complement format.

Thanks,

Weidong
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