[USRP-users] USRP X310 clock options

Marcus Müller marcus.mueller at ettus.com
Tue Mar 15 06:12:35 EDT 2016


Dear Hervé,

Oh, I'll need to look that discussion up; I'm sorry that I didn't follow
up on it :( will read that later on today!

> Concerning the CBX, I was thinking about the lowest sampling rate
possible because of the data transfer rate on the 10Gbit Ethernet interface!

Ah, ok, so yes, if you want to have the 120 MHz analog bandwidth and can
live with the filter effects at the band edges, yes, MCR=120 MHz will be
your choice.

Technologically, neglecting overhead, the 10GE link can carry a total of
312.5 MS/s in each direction.So, if you only need 1 CBX-120's worth of
RX bandwidth, you can do full 200MS/s without problem. However,
2x200MS/s won't be possible.

Thinking about this: If doing FPGA design work is possible for you, you
can do a couple of things:
* Using RFNoC, you could write a sample width reducer, giving you 8 bit
samples. You lose accuracy, but gain a factor of 2 in possible
bandwidth, making 2x 200MS/s possible
* Using RFNoC and a polyphase resampler, you could implement something
2/3 resampler, to generate a 133.3̅ MS/s signal. Considering the analog
filter already works pretty well, the core filter can be pretty relaxed,
and hence, short.

Best regards,
Marcus


On 15.03.2016 10:44, Hervé BOEGLEN wrote:
> Dear Marcus,
>
> The reason for my question is that I was trying to obtain a 80MHz
> sample rate with the X310. This is only for a comparison with radio
> channel measurements we made with another measurement device.
>
> Concerning the CBX, I was thinking about the lowest sampling rate
> possible because of the data transfer rate on the 10Gbit Ethernet
> interface! This reminds me that I did not give you the results about
> my data transfer rates tests after my question on the list
> mid-February. I got up to 100Msps with the following setup:
>
> * Numbers format: with Matlab I generate my file in Q15 format (Ettus
> sc16). This means 2 bytes per channel.
> * Following your suggestion I generate quite huge files (typically
> bigger than 500Mbytes)
>
> I noticed the number format problem when I tried to write a file on a
> SSD (with rx_samples_to_file). With fc32 at 100Msps UHD warns you that
> you will need a 800Mbytes/s capable disk... With sc16 it goes down to
> 400Mbytes/s which is OK with my SSD.
>
> Anyway, thanks again to Claudio Cicconetti and you for helping me to
> solve this issue!
>
> Best regards
>
> Hervé
>
>
> Le 15/03/2016 09:49, Marcus Müller via USRP-users a écrit :
>> Dear Hervé,
>>
>> bus_clk != master_clock_rate
>>
>> The bus_clk, as far as I know, is fixed, and can't really be lowered
>> (because that would break the interaction with the 10GE phy). It's
>> generated from a 125 MHz clock. If I remember correctly, it was Sylvain
>> who wanted to speed up some tests, and then, for production purposes,
>> restore the clock to its original speed.
>>
>> master_clock_rate is more or less a "higher-level" view on things;
>> physically, it's represented by the different clock frequencies the
>> LMK04816 can produces on FPGA_CLK_p / _n and the DB{0,1}_ADC_REFCLK_p
>> /_n as well as the DB{0,1}_DAC_REFCLK_p /_n pins.
>>
>> So, what's the reason for your question? Maybe we can help you
>> better/faster when discussing potential modifications with respect to a
>> known "goal".
>>> Another question related to clock rates on X310. If you want to use
>>> the full RF bandwith of the CBX-120 the only solution is to use a
>>> master clock rate of 120MHz, am I right? Indeed, I have noticed that
>>> it is not possible to get a fractional decimation rate with the
>>> current implementation of UHD.
>> You could as well use a 200 or 184.32 MHz MCR with a sampling rate of
>> the same value. Notice that the 120MHz bandwidth of the CBX is defined
>> by the analog baseband filtering, and that has finite steepness at the
>> cutoff frequency, so you'd not do so bad having a bit of "spectrum
>> reserve" on each side to avoid aliasing.
>>
>> Best regards,
>> Marcus
>>
>>
>> On 15.03.2016 08:32, Hervé BOEGLEN via USRP-users wrote:
>>> Dear all,
>>>
>>> According to Ettus documentation, X310 master clock rates are hard
>>> coded in UHD and are 200MHz, 184,32MHz and 120MHz.
>>>
>>> However, someone mentioned in a recent post that it was possible to
>>> use bus_clk which is at 166,67MHz. How can you do that? Which option
>>> do you use? When I change the master clock rate I use
>>> "master_clock_rate = value".
>>>
>>> Another question related to clock rates on X310. If you want to use
>>> the full RF bandwith of the CBX-120 the only solution is to use a
>>> master clock rate of 120MHz, am I right? Indeed, I have noticed that
>>> it is not possible to get a fractional decimation rate with the
>>> current implementation of UHD.
>>>
>>> Thanks in advance
>>>
>>> Hervé
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
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