[USRP-users] USRP X310 clock options

Marcus Müller marcus.mueller at ettus.com
Tue Mar 15 04:49:18 EDT 2016


Dear Hervé,

bus_clk != master_clock_rate

The bus_clk, as far as I know, is fixed, and can't really be lowered
(because that would break the interaction with the 10GE phy). It's
generated from a 125 MHz clock. If I remember correctly, it was Sylvain
who wanted to speed up some tests, and then, for production purposes,
restore the clock to its original speed.

master_clock_rate is more or less a "higher-level" view on things;
physically, it's represented by the different clock frequencies the
LMK04816 can produces on FPGA_CLK_p / _n and the DB{0,1}_ADC_REFCLK_p
/_n as well as the DB{0,1}_DAC_REFCLK_p /_n pins.

So, what's the reason for your question? Maybe we can help you
better/faster when discussing potential modifications with respect to a
known "goal".
>
> Another question related to clock rates on X310. If you want to use
> the full RF bandwith of the CBX-120 the only solution is to use a
> master clock rate of 120MHz, am I right? Indeed, I have noticed that
> it is not possible to get a fractional decimation rate with the
> current implementation of UHD. 
You could as well use a 200 or 184.32 MHz MCR with a sampling rate of
the same value. Notice that the 120MHz bandwidth of the CBX is defined
by the analog baseband filtering, and that has finite steepness at the
cutoff frequency, so you'd not do so bad having a bit of "spectrum
reserve" on each side to avoid aliasing.

Best regards,
Marcus


On 15.03.2016 08:32, Hervé BOEGLEN via USRP-users wrote:
> Dear all,
>
> According to Ettus documentation, X310 master clock rates are hard
> coded in UHD and are 200MHz, 184,32MHz and 120MHz.
>
> However, someone mentioned in a recent post that it was possible to
> use bus_clk which is at 166,67MHz. How can you do that? Which option
> do you use? When I change the master clock rate I use
> "master_clock_rate = value".
>
> Another question related to clock rates on X310. If you want to use
> the full RF bandwith of the CBX-120 the only solution is to use a
> master clock rate of 120MHz, am I right? Indeed, I have noticed that
> it is not possible to get a fractional decimation rate with the
> current implementation of UHD.
>
> Thanks in advance
>
> Hervé
>
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