[USRP-users] AD9361 Fast Lock

Rigney, Kevin E kevin.e.rigney at lmco.com
Wed Mar 2 17:49:18 EST 2016


Michael,

Unfortunately the FPGA control is a requirement of our design as the FPGA needs to be able to quickly select one of the eight bands. At this point having the FPGA send SPI commands to tune would be too complex. If we can't get the fast lock working that may be a path we have to take.

-Kevin

From: Michael West [mailto:michael.west at ettus.com] 
Sent: Wednesday, March 02, 2016 5:15 PM
To: Rigney, Kevin E (US) <kevin.e.rigney at lmco.com>
Cc: usrp-users at lists.ettus.com
Subject: EXTERNAL: Re: [USRP-users] AD9361 Fast Lock

Hi Kevin,
Understood.  I just wanted to mention it in case it could save you some effort.  The latest development code does offer tune times of ~0.8ms (at a master clock rate of 32e6) as well as exposing parameters to enable/disable RX DC offset calibration (a major cause of tune latency) and control the width of the window for which the calibrations are valid (default is 100 MHz, which means that calibrations are run each time you tune 100 MHz away from the last calibration frequency).  Let me know if you want to try it out and I will send you a UHD patch privately.

Regards,
Michael

On Wed, Mar 2, 2016 at 1:06 PM, Rigney, Kevin E <kevin.e.rigney at lmco.com> wrote:
Michael,

We’re developing custom FPGA code that uses the USRP to scan extremely quickly (sub-ms tuning time is required). The limit of 8 frequencies is OK for our application. The frequencies could be anywhere in the AD9361 tuning range. We understand that there will be potential issues with the DUC/DDC chain but right now we just need to get something working.

Currently we're using the SPI to program and select a fast lock frequency but the final implementation will have the FPGA toggle the CTRL_IN pins on the AD9361 to select the fast lock frequency.

-Kevin


From: Michael West [mailto:michael.west at ettus.com]
Sent: Wednesday, March 02, 2016 4:01 PM
To: Rigney, Kevin E (US) <kevin.e.rigney at lmco.com>
Cc: usrp-users at lists.ettus.com
Subject: EXTERNAL: Re: [USRP-users] AD9361 Fast Lock

Hi Kevin,
We are aware of the feature, but have not experimented with it yet.  IIRC, the fast lock feature can store up to 8 frequencies so it is good if you are using only a few frequencies but not so good if you need to sweep a lot of frequencies.  We currently have UHD code in development that significantly reduces the tuning time for AD9361, so it may not be necessary for you to do all the work to get the fast lock feature working.  How many frequencies does your application use, how far apart are they, and how fast do you need to retune?
Regards,
Michael

On Wed, Mar 2, 2016 at 11:53 AM, Rigney, Kevin E via USRP-users <usrp-users at lists.ettus.com> wrote:
Hello,

Has anyone gotten fast lock working for the AD9361 Chip (E310 and B200)? I'm trying to implement fast lock and am having issues. I've added what I think is the appropriate code in all of the ad9361 files and the *impl.cpp files to add function calls to the tree. I believe I'm just not sending the correct data over the SPI bus.

Thanks,

Kevin Rigney


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