[USRP-users] timing issues with RFNoC block

Sylvain Munaut 246tnt at gmail.com
Wed Mar 2 10:35:18 EST 2016


> I seem to be having some timing issues with an RFNoC block.  My block
> worked, I made some significant changes, it stopped working, and then I
> rolled back and the block continued to not work.  I played with things for
> about a week until I got it to work again.  I made one minor change and
> suddenly things didn't work again.  This makes me think that I am right up
> against some sort of threshold somewhere (most probably timing) and it
> sometimes works, and other times doesn't (though the block always "runs").
> So my question is, is there a good methodology for working on the timing of
> a particular block within your larger RFNoC VIvado project?

If the design met the timing when building (as reported by xilinx
static timing analyzer) and it still exhibits random behaviour, then
there is probably a bug in your logic and it doesn't entirely comply
with the AXI stream specs. (like not handling 'busy' output or holes
in the 'valid' at the input or things like that).

I usually test my logic in simulation against 'random' input/output
patterns (forcing valid=0 at the input randomly and forcing 'ready=0'
at the output randomly). and check the output is still the expected



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