[USRP-users] Order of CIC and Half Band Filters USRP N210
matt at ettus.com
Mon Aug 8 15:32:46 EDT 2016
The CIC is a fourth order design.
On Mon, Aug 8, 2016 at 12:29 PM, Richard Bell via USRP-users <
usrp-users at lists.ettus.com> wrote:
> Thanks Marcus,
> Do you know how many stages there are in the CIC filter?
> On Mon, Aug 8, 2016 at 12:02 PM, Marcus Müller <marcus.mueller at ettus.com>
>> Hi Rich,
>> The way it's built right now actually is that cascade of two HBs and one
>> Which means that IDF your decimation is even, but not dividable by four,
>> one half band will be enabled, the other bypassed, and the uneven factor
>> will be done by the CIC. If your decimation is dividable by four, both half
>> bands will be at work and the rest will be done by the CIC, and if it's
>> odd, then only the CIC will be used to decimate.
>> However, with minimal host code modifications, adding another settings
>> register and implementing additional halfbands, you should be able to
>> change that; of course, you can also change the taps.
>> You'll note, however, that those are hardcoded into the filters, so
>> you'll need to build your own FPGA image.
>> Best regards,
>> Am 8. August 2016 20:29:31 MESZ, schrieb Richard Bell via USRP-users <
>> usrp-users at lists.ettus.com>:
>>> Hi all,
>>> I was wondering if the order of the CIC filter and Half Band filters is
>>> fixed in the USRP N210 FPGA chain? I am interpreting the 1-to-128 labelled
>>> block in the attached block diagram as the CIC portion of the filtering. Is
>>> this strictly the case or could there be additional half band filters
>>> implemented in there?
>>> If an even divisor of 100 MHz is chosen as the output sample rate, will
>>> the 1-to-128 block be a cascade of half band filters?
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
>> Sent from my Android device with K-9 Mail. Please excuse my brevity.
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