[USRP-users] Another question regarding uhd_usrp_probe, NoC Script and my RFNoC XML file
martin.braun at ettus.com
Wed Oct 28 17:59:32 EDT 2015
that's a good idea, and we've had that idea ourselves. It's not quite as
simple as it sounds, so don't expect this to happen anytime in the near
future (there are other things with higher priority).
However, if you use the Modelsim testbenches, you can get pretty far.
You can write command packages that will set registers and see what's
going on inside your core. Writing the XML files for GNU Radio and
NocScript shouldn't be a difficult task -- it just maps settings to
registers, so once you're confident your block works, writing your
NocScript is hopefully not a development bottleneck.
On 28.10.2015 12:30, Swanson, Craig wrote:
> Jonathon and Martin,
> What would be ideal is if I could write up my XML file so when I run
> uhd_usrp_probe --arg no_load_fpga that it fires up the crossbar
> and comes close to imitating my system verilog testbench file in the
> lib/rfnoc directory. I would like to read and write to certain register
> locations several times, and even send packets of data which I could
> trigger on using Chipscope. That would allow me to have to avoid going
> through the somewhat time consuming integration with gnuradio.
> Would that be possible or could you modify or create another
> uhd_usrp_probe utility that would excercise the FPGA with commands
> similar to the System verilog testbench?
> I have sent you several emails lately so I hope I didn't already ask you
> this question.
> *Craig F. Swanson*
> */Research Engineer II
> */Information and Communications Laboratory/*
> */Communications, Systems, and Spectrum Division/*
> /Georgia Tech Research Institute/
> /Room 560
> 250 14th St NW
> /Atlanta, GA 30318/
> /Cell: 770.298.9156/
More information about the USRP-users