[USRP-users] Error in x300 generation fpga bit file

mojtaba rostami mrbilandi at yahoo.com
Wed Oct 28 03:46:10 EDT 2015


Hi,
When i generate x300 FPGA Bit file via "make X300_XGS GUI=1" encounter to this DRC error: 
But when i generate without GUI it generate successfully bit file!
[DRC 23-20] Rule violation (RTSTAT-3) Unplaced terminals on net - 486 net(s) have unplaced terminals. The problem bus(es) and/or net(s) are CPRI_CLK_OUT_P, lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/ChinchRegisterAccessx/Mcount_bTimeoutCounterReg_cy[9], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/Mcompar_HandleArbiterRequests.bFifoFullCountDelay2[9]_HandleArbiterRequests.bFifoFullCountDelay[9]_LessThan_82_o_cy[4:0], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/Mcount_HandleArbiterRequests.bEvictionCounter_cy[6], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/Mcount_bDataWordCounter_cy[6], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchInterfaceDmaRegistersx/Maccum_bSatcr_cy[30], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchInterfaceDmaRegistersx/Mcompar_GND_565_o_SatcrRegister.bSatcrNx[31]_LessThan_22_o_cy[9:0], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchInterfaceDmaRegistersx/Mmux_bSatcr[31]_GND_565_o_mux_19_OUT_rs_cy[30], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchInterfaceDmaRegistersx/Msub_GND_565_o_GND_565_o_sub_24_OUT<9:0>_cy[8], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/Mcompar_HandleArbiterRequests.bFifoFullCountDelay2[9]_HandleArbiterRequests.bFifoFullCountDelay[9]_LessThan_82_o_cy[4:0], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/Mcount_HandleArbiterRequests.bEvictionCounter_cy[6], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/Mcount_bDataWordCounter_cy[6], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchInterfaceDmaRegistersx/Maccum_bSatcr_cy[30], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchInterfaceDmaRegistersx/Mcompar_GND_576_o_SatcrRegister.bSatcrNx[31]_LessThan_22_o_cy[9:0], lvfpga_chinch_inst/EttusUsrpChinchWrapperx/ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchInterfaceDmaRegistersx/Mmux_bSatcr[31]_GND_576_o_mux_19_OUT_rs_cy[30] (the first 15 of 347 listed).


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