[USRP-users] RFNoC Tutorial - Synthesis error

Jonathon Pendlum jonathon.pendlum at ettus.com
Fri Oct 23 15:20:07 EDT 2015

Hi Nicolas,

We are now using Vivado 2015.2 for FPGA builds so that is the source of
your issue. Make sure to run 'make cleanall' before you try to build again.
I also updated the RFNoC wiki as it did have old instructions for the
previous release. Thanks for catching that!


On Fri, Oct 23, 2015 at 5:19 AM, Nicolas Cuervo Benavides via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hi all!
> I'm a newbie in RFNoc. In the lab we have Vivado 2014.4 installed (only
> with evaluation license so far), Ubuntu 14.04 LTS and the device is an
> X310. For a quick start I went for the tutorial that can be found under the
> following link:
> http://www.trondeau.com/s/3-pendlum_jonathon-rfnoc_tutorial_fpga.pdf
> In which I get until the building of the tutorial image my typing
> $ make X310_RFNOC_HGS
> although in the tutorial it says make X310_HGS_RFNOC, but I just assumed
> the name of the file changed on the continuous development in which RFNoc
> undergoes.
> At this point, after a couple of minutes, I get the error regarding the
> 10G ethernet:
> ERROR: [Common 17-69] Command failed: * IP definition 'Ten Gigabit
> Ethernet PCS/PMA (10GBASE-R/KR) (6.0)' for IP 'ten_gig_eth_pcs_pma' was not
> found in the IP Catalog.
> Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl
> command 'report_ip_status' for more information.
>     while executing
> "open_example_project -force -dir . [get_ips $ip_name]"
>     invoked from within
> "if [string match $gen_example_proj "1"] {
>     puts "BUILDER: Generating Example Design..."
>     open_example_project -force -dir . [get_ips $ip_name]
> }"
>     (file "/uhd/fpga-src/usrp3/top/../tools/scripts/viv_generate_ip.tcl"
> line 30)
> I go to Vivado (2014.4, so far only with evaluation license) and first I
> see this at opening:
>  [Project 1-19] Could not find the file
> '/uhd/fpga-src/usrp3/lib/timing/pps.v'.
> which is stated as warning, but I don't really know if it's related to the
> error I'm receiving. Then, I see that the IP ten_gig_eth is "locked", and
> the software recommends me to check the catalog for a replacement. However,
> the replacement available doesn't allow me to continue the synthesis, as it
> needs to be purchased (apparently my license does not include it).
> I try just to disable the module directly in Vivado, but didn't see a
> difference.
> Any Ideas of how can I continue with this tutorial?
> Thank you all in advance!
> Best Regards
> --
> Nicolás Cuervo Benavides
> Handy: +49 157 70476855
> Electric and Electronic Engineering department.
> Electronic Engineering
> Universidad Nacional de Colombia
> --
> Student M.Sc. Information and Communication Technology
> Karlsruher Institut für Technologie
> Karlsruhe, Baden Würtemberg, Germany
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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