[USRP-users] E310: signal processing possible on the FPGA

Martin Braun martin.braun at ettus.com
Tue Oct 20 12:51:08 EDT 2015


On 19.10.2015 16:41, Chris Stankevitz via USRP-users wrote:
> I would like to run a filter which essentially averages the power of
> the signal over the past x samples.  If and when a threshold is
> exceeded, I would like the ARM CPU to be given the raw samples for
> subsequent high-level processing.
> 
> I know how to perform this process entirely on the ARM CPU: use the
> UHD library to grab the raw samples and perform the power-calculating
> filter on the ARM CPU.  But I'm not sure the ARM CPU will be able to
> keep up as I increase the sample rate (ideally to 10 MHz).
> 
> Is it possible for the USRP E310 to perform this kind of signal
> processing on "the FPGA" instead of on "the ARM"?  If so, by what
> mechanism will the results of this processing (the average power in
> my example) be made available to the UHD client application?  Is it
> possible that, using UHD, I am delivered 3 scalars for each sample:
> real, imaginary, and the result of some filter e.g. avg power?
> 
> I've been assuming that this processing must occur on the ARM CPU
> until a few minutes ago a colleague wondered aloud "I think the E310
> can run some flow graphs on the FPGA itself at the full sample
> rate".

Yes, this is true. We are working on a framework called 'RFNoC' which
will let you do this with a minimum of hassle (some FPGA work is still
required, though). See also
http://www.ettus.com/sdr-software/detail/rf-network-on-chip.

RFNoC is not yet released as part of an official UHD release, but it's
already quite stable and many people have built applications using it.
You'll find a small getting started guide here:
https://github.com/EttusResearch/uhd/wiki, and there's also some videos
on RFNoC here:
http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr or as
part of last year's GNU Radio conference:
http://www.trondeau.com/grcon15-presentations/ (look for RFNoC).

Cheers,
Martin




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