[USRP-users] E310 RFNoC and Vivado 2015.2 Build Problem

Michael Wentz mchlwntz at gmail.com
Fri Oct 2 07:50:23 EDT 2015


>From the announcement in September it seemed like rfnoc-devel has been
updated to Vivado 2015.2, so I just upgraded. Now I am having difficulty
making E310_RFNOC from scratch (it worked fine under 2014.4). The problem
seems to be related to the divide_int16_int32 IP. Relevant error messages
from the log are below.

Seems like these errors occur when IP has been generated with an older
version of Vivado. The file usrp3/lib/ip/divide_int16_int32.xci indicates
it was made with 2014.4 - does it still need to be updated to 2015.2? If
not, any suggestions to get this working?

Thanks,
Michael

- - - - - - - - - -

WARNING: [IP_Flow 19-3664] IP 'divide_int16_int32' generated file not found
'/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int16_int32/divide_int16_int32_funcsim.vhdl'.
Please regenerate to continue.

WARNING: [IP_Flow 19-2162] IP 'divide_int16_int32' is locked:
* IP definition 'Divider Generator (5.1)' for IP 'divide_int16_int32' has a
different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl
command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'

3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [Vivado 12-3435] The given sub-design is up-to-date, no action was
taken.  If a regeneration is desired, use the '-force' option:
/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32.xci

ERROR: [Runs 36-335]
'/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int16_int32/divide_int16_int32.dcp'
is not a valid design checkpoint
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