[USRP-users] Add a module in the USRP B210 FPGA

Ashish Chaudhari ashish.chaudhari at ettus.com
Thu Jul 23 17:21:55 EDT 2015


Hello Gaëlle Clot,

1.       How to add a custom module in usrp3 architecture ?


The FPGA build system is all Makefile based and new sources just need to be
added to a Makefile.srcs file in the directory that you choose to add your
source. All you have to do is create your new verilog file, copy it over to
 https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200 and add
it to
https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/Makefile.b200.inc#L64.
If you are adding more generic code then it should probably live in the
https://github.com/EttusResearch/fpga/blob/master/usrp3/lib directory and a
corresponding Makefile.srcs file.

2.       Where can I instantiate my module ? in radio_b200 after the
> ddc_chain, in b200_core or b200 before the GPIF2_slave_fifo32 ?


I would recommend adding your module either in radio_b200 or right next to
radio_b200. By the time the data reaches the GPIF interface, it has already
been packetized.

3.       Do I have to replace the I and Q signals by my detection signal or
> can I send all the 3 of them to the host ?


Adding a 3rd stream of data is much harder to achieve because that requires
parallel changes to the UHD (the software driver). If you can replace the
existing I and Q signals, I would recommend doing that. If you don't care
about dynamic range you could possibly use one bit from your sample as the
"pulse edge detected" bit and on the host side manually extract it. It's a
bit hacky but it should work. Here are some tap points that would interest
you:
Sample Data:
https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/radio_b200.v#L21
Data right after it is packetized:
https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/radio_b200.v#L25
Data right before it is packetized:
https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/radio_b200.v#L434

Hope that helps. And sorry for the delay!

Regards,

*Ashish Chaudhari* | Senior Software Engineer | High Frequency Measurements
- RF
Ettus Research, *A National Instruments Company*
ashish.chaudhari at ettus.com

On Thu, May 21, 2015 at 6:16 AM, CLOT Gaelle via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Hi
>
>
>
> I’m using a B210 board to determinate the Time of Arrival (ToA) of a radar
> signal.
>
> I first used GRC to do it (see attachment).
>
> In this flow graph, a first channel is used to emit a pulse train in order
> to simulate a radar signal.
>
> The second channel receives this signal which is then processed by GRC.
>
> The ToA corresponds to the time of a pulse leading edge.
>
> So what I did is create a signal which is set to 1 when a pulse leading
> edge is detected.
>
> The time stamp corresponding to this signal =1 is the ToA.
>
>
>
> Now I would like to implement this directly in the FPGA but I don’t know
> how to achieve that…
>
> 1.       How to add a custom module in usrp3 architecture ?
>
> 2.       Where can I instantiate my module ? in radio_b200 after the
> ddc_chain, in b200_core or b200 before the GPIF2_slave_fifo32 ?
>
> 3.       Do I have to replace the I and Q signals by my detection signal
> or can I send all the 3 of them to the host ?
>
>
>
> Thanks for your help
>
>
>
> Best regards
>
>
>
> Gaëlle Clot
>
>
>
>
>
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/attachments/20150723/fb8eb8c8/attachment-0002.html>


More information about the USRP-users mailing list