[USRP-users] b210 fpga source makefile trouble

Ian Buckley ianb at ionconcepts.com
Wed Jul 15 13:47:40 EDT 2015


What you should see is pasted below…what's with running the job as root (sudo)?
Note that in the very first line your log has no ISE version info…makes me wonder if the ISE setup script has been run in this shell.
>>>  `source <install_dir>/Xilinx/14.7/ISE_DS/settings64.sh` (64-bit platform)

I'd recommend a clean shell thats logged in as user you need to work as, sourcing the Xilinx script, then running make B210.
A quick sanity test might be: which xtclsh
Which for a default install will give: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh


-----log output-------

ISE Version: Release 14.7 - xtclsh P.20131013 (lin64)
make -f Makefile.b200.inc bin NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="B210=1 "
make[1]: Entering directory `/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/top/b200'
build-B210//b200.xise
xtclsh /disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/top/tcl/ise_helper.tcl ""
>>> Creating project: build-B210//b200.xise
Changed current working directory to the project directory:
"/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/top/b200/build-B210" 
>>> Setting: Project[family] = Spartan6
>>> Setting: Project[device] = XC6SLX150
>>> Setting: Project[package] = fgg484
>>> Setting: Project[speed] = -3
>>> Setting: Project[top_level_module_type] = HDL
>>> Setting: Project[synthesis_tool] = XST (VHDL/Verilog)
>>> Setting: Project[simulator] = ISE Simulator (VHDL/Verilog)
WARNING:TclTasksC - The value(s) of this property has been changed in the
   current release to "ISim (VHDL/Verilog)". The property value has been set to
   "ISim (VHDL/Verilog)". Please update your script to use the new value to
   avoid this message in the future.
>>> Setting: Project[Preferred Language] = Verilog
>>> Setting: Project[Enable Message Filtering] = FALSE
>>> Setting: Project[Display Incremental Messages] = FALSE
>>> Adding source to project: /disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/top/b200/b200.v
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/disk2/ianb/ettus/fpgadev-b200/fpgadev/usrp3/top/b200/b200.v" into library
   work

On Jul 15, 2015, at 10:27 AM, Justin Tallon . <tallonj at tcd.ie> wrote:

> 
> after entering _>sudo make B210
> 
> I have the following error 
> 
> ISE Version: 
> make -f Makefile.b200.inc bin NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="B210=1"
> make[1]: Entering directory `/home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200'
> build-B210//b200.xise
> xtclsh /home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/tcl/ise_helper.tcl ""
> build-B210//b200.bin
> xtclsh /home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/tcl/ise_helper.tcl "Generate Programming File" 2>&1 | tee build-B210//build.log
> tee: build-B210//build.log: No such file or directory
> make[1]: *** [build-B210//b200.bin] Error 1
> make[1]: Leaving directory `/home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200'
> make: *** [B210] Error 2
> 
> 
> 
> On 15 July 2015 at 18:20, Ian Buckley <ianb at ionconcepts.com> wrote:
> What happens if you try a full build (make B210) which will also incidentally generate b200.xise?
> 
> On Jul 15, 2015, at 10:15 AM, "Justin Tallon ." <tallonj at tcd.ie> wrote:
> 
>> Hey Ian!
>> 
>> Thanks for your help on this.
>> 
>> I mistyped the email when I wrote ../top/B200/build_b210/ 
>> There is no folder at the location specified by the log output.
>> 
>> ie at  /home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200/build-B210/b200.xise
>> 
>> also I did a system wide search for b200.xise  and it exists no where on the system.
>> 
>> Regards,
>> Justin
>> 
>> 
>> On 15 July 2015 at 18:06, Ian Buckley <ianb at ionconcepts.com> wrote:
>> See below:
>> 
>> On Jul 15, 2015, at 9:55 AM, "Justin Tallon . via USRP-users" <usrp-users at lists.ettus.com> wrote:
>> 
>>> Hey!
>>> 
>>> I am trying to bui;d the b210 fpga .bin file from source by using the makefile to generate a .xise project file.
>>> 
>>> I have followed the instructions in the README file in the fpga-src folder ie
>>> ## Build Instructions (Xilinx ISE only)
>>> 
>>> - Download and install [Xilinx ISE 14.7](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v2012_4---14_7.html)
>>>   + You may need to acquire an implementation license to build some USRP designs.
>>>     Please check the Xilinx Requirements document above for the FPGA technology used by your USRP device.
>>> 
>>> - To add xtclsh to the PATH and to setup up the Xilinx build environment run
>>>   + `source <install_dir>/Xilinx/14.7/ISE_DS/settings64.sh` (64-bit platform)
>>>   + `source <install_dir>/Xilinx/14.7/ISE_DS/settings32.sh` (32-bit platform)
>>> 
>>> - Navigate to `usrp3/top/{project}` where cproject is:
>>>   + b200: For USRP B200 and USRP B210
>>> 
>>> - To build a binary configuration bitstream run `make <target>`
>>>   where the target is specific to each product. To get a list of supported targets run
>>>   `make help`.
>>> 
>>> - The build output will be specific to the product and will be located in the
>>>   `usrp3/top/{project}/build` directory. Run `make help` for more information.
>>> 
>>> 
>>> however, when I execute 
>>> $ make B210 PROJECT_ONLY=1
>>> 
>>> it seems to execute sucessfully, outputting the following:
>>> ISE Version: 
>>> make -f Makefile.b200.inc proj NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="B210=1"
>>> make[1]: Entering directory `/home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200'
>>> build-B210//b200.xise
>>> xtclsh /home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/tcl/ise_helper.tcl ""
>>> make[1]: Leaving directory `/home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200'
>> 
>> Here's the log line showing where it's generated the .xise file.
>> 
>>> Generated /home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200/build-B210/b200.xise
>>> 
>>> Project Generation DONE ... B210
>>> 
>>> 
>> There's no directory with a capitalized "B200" only "b200".
>> 
>>> but the directory ../top/B200/build_b210/ does not actually appear and cannot be found anywhere on the system, even thought the output says it have been created
>>> 
>>> 
>>> Any thoughts?
>>> Thanks!
>>> Justin.
>>> 
>>> 
>>> -- 
>>> __________________________________________
>>> Regards,
>>> Justin Tallon
>>> CTVR / The Telecommunications Research Centre
>>> Dunlop Oriel House
>>> Trinity College
>>> Dublin 2
>>> t: +353 1 896 4243
>>> m:+353 860670753
>>> http://www.ctvr.ie/
>>> 
>>> 
>>> _______________________________________________
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>> 
>> 
>> 
>> 
>> -- 
>> __________________________________________
>> Regards,
>> Justin Tallon
>> CTVR / The Telecommunications Research Centre
>> Dunlop Oriel House
>> Trinity College
>> Dublin 2
>> t: +353 1 896 4243
>> m:+353 860670753
>> http://www.ctvr.ie/
>> 
>> 
> 
> 
> 
> 
> -- 
> __________________________________________
> Regards,
> Justin Tallon
> CTVR / The Telecommunications Research Centre
> Dunlop Oriel House
> Trinity College
> Dublin 2
> t: +353 1 896 4243
> m:+353 860670753
> http://www.ctvr.ie/
> 
> 

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