[USRP-users] b210 fpga source makefile trouble

Ian Buckley ianb at ionconcepts.com
Wed Jul 15 13:06:35 EDT 2015


See below:

On Jul 15, 2015, at 9:55 AM, "Justin Tallon . via USRP-users" <usrp-users at lists.ettus.com> wrote:

> Hey!
> 
> I am trying to bui;d the b210 fpga .bin file from source by using the makefile to generate a .xise project file.
> 
> I have followed the instructions in the README file in the fpga-src folder ie
> ## Build Instructions (Xilinx ISE only)
> 
> - Download and install [Xilinx ISE 14.7](http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools/v2012_4---14_7.html)
>   + You may need to acquire an implementation license to build some USRP designs.
>     Please check the Xilinx Requirements document above for the FPGA technology used by your USRP device.
> 
> - To add xtclsh to the PATH and to setup up the Xilinx build environment run
>   + `source <install_dir>/Xilinx/14.7/ISE_DS/settings64.sh` (64-bit platform)
>   + `source <install_dir>/Xilinx/14.7/ISE_DS/settings32.sh` (32-bit platform)
> 
> - Navigate to `usrp3/top/{project}` where cproject is:
>   + b200: For USRP B200 and USRP B210
> 
> - To build a binary configuration bitstream run `make <target>`
>   where the target is specific to each product. To get a list of supported targets run
>   `make help`.
> 
> - The build output will be specific to the product and will be located in the
>   `usrp3/top/{project}/build` directory. Run `make help` for more information.
> 
> 
> however, when I execute 
> $ make B210 PROJECT_ONLY=1
> 
> it seems to execute sucessfully, outputting the following:
> ISE Version: 
> make -f Makefile.b200.inc proj NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="B210=1"
> make[1]: Entering directory `/home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200'
> build-B210//b200.xise
> xtclsh /home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/tcl/ise_helper.tcl ""
> make[1]: Leaving directory `/home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200'

Here's the log line showing where it's generated the .xise file.

> Generated /home/nodeuser/data/alt_iris/uhd_fpga/uhd/fpga-src/usrp3/top/b200/build-B210/b200.xise
> 
> Project Generation DONE ... B210
> 
> 
There's no directory with a capitalized "B200" only "b200".

> but the directory ../top/B200/build_b210/ does not actually appear and cannot be found anywhere on the system, even thought the output says it have been created
> 
> 
> Any thoughts?
> Thanks!
> Justin.
> 
> 
> -- 
> __________________________________________
> Regards,
> Justin Tallon
> CTVR / The Telecommunications Research Centre
> Dunlop Oriel House
> Trinity College
> Dublin 2
> t: +353 1 896 4243
> m:+353 860670753
> http://www.ctvr.ie/
> 
> 
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