[USRP-users] Aurora core possible with an X310?

Jason Matusiak jason at gardettoengineering.com
Tue Jul 14 15:18:33 EDT 2015


Ian, Good points.  I guess I haven't really thought if there is "host
processing".  The RF will be coming from/to something connected to the
USRP, but if the USRP is just a front end that samples, mixes down/up,
and does the Aurora conversion, I guess that the GRC won't have a "host"
in that sense (unless allow for changing the IF frequency on the fly).

I wouldn't say considerable in-house FPGA skills, but I've been the
working on our in-house testbed emulator, so I would be the one working
on the FPGA block for the X310.

>I presume you reconstruct the sampling clock locally in the FPGA from the Aurora clock, the frontend being the clock 
>source. That would also mean a few changes in X3x0, but nothing too hard.
I'm not really sure, I haven't thought that far ahead.  Our current
system has 10MHz clocks distributed throughout our system to all our
boards for clock syncing.  That obviously won't work the exact same way
with the USRP.

So it sounds like your are saying to take the X310 project, and ignore
the RFNoC side of things and just rework the Vivado project itself to do
what I need?  That about right?  If so, what is the best way to work on
it?  With the Ettus makefile build process being so tightly coupled with
the TCL scripts, it hasn't appeared very straightforward to bring up the
Vivado GUI and develop from within there (which would certainly be
easiest since I can't really visualize the FPGA code structure yet).




More information about the USRP-users mailing list