[USRP-users] Aurora core possible with an X310?

Ian Buckley ianb at ionconcepts.com
Tue Jul 14 12:45:18 EDT 2015

Perhaps I'm missing something here but if you have a system thats standalone with no host based signal processing (..and I'm assuming thats whats implied by a FPGA only flow graph) then you have no motivation to use RFNoC at all.
You are already going to have to deal with code merges anyhow if you wish to track further Ettus FPGA development because replacing one of the Ethernet PHY's with the the Aurora IP is well beyond the scope of RFNoC.
Assuming considerable in house FPGA skills since you already maintain a proprietary FPGA design, it's not a very hard design problem to tap sample streams in the X3x0 radio and tunnel them via the Auroa link.
I presume you reconstruct the sampling clock locally in the FPGA from the Aurora clock, the frontend being the clock source. That would also mean a few changes in X3x0, but nothing too hard.
You can probably can just leave all idle Ethernet MAC and packet logic associated with the now reassigned SFP+ and just cut the wiring neatly between PHY and MAC if you would like to avoid spending time removing no unused logic, which might also be better from a software point of view.There might be one or 2 little firmware tweaks needed to deal with missing MDIO registers in the PHY but it would be trivial work.

I'm sure there are some details that I haven't thought of, but its a very practical project to attempt.

On Jul 14, 2015, at 9:11 AM, Jason Matusiak via USRP-users <usrp-users at lists.ettus.com> wrote:

>> AFAICT the SFP+ connectors on the X310 are directly connected to MGTs
>> on the FPGA. So you could remove one of the ethernet SFP+ connection
>> from the fpga code, then reuse that SFP+ to directly put a fiber
>> transceiver and an Aurora core inside.
>> And that could indeed be a RFNoC block so you can easily direct
>> traffic to it or to the host. (note that fpga only flow graph are not
>> supported atm, but should be in the future).
> Hmm, this is very interesting.  This would allow for a potential drop-in
> replacement, that would be awesome.  I would need to mix down to IF
> first, but that shouldn't be too crazy.  
> I guess I forgot that we couldn't use FPGA only flow graphs, how far out
> is that hopeful implementation?
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