[USRP-users] fpga build win7
ianb at ionconcepts.com
Fri Jul 10 12:20:42 EDT 2015
Looking at that Lisa I can not but help think that the problem is which ever Unix emulation package you are using for Windows. Ettus builds no FPGA's under Windows so these scripts aren't tested for that purpose.
There are a few USRP users who do use Windows as a build platform, and perhaps they can add more expert advice?
On Jul 10, 2015, at 1:09 AM, Lisa-Marie Faller via USRP-users <usrp-users at lists.ettus.com> wrote:
> attached is now a screenshot of the output and build.log after a second try of 'make ...'.
> On 2015-07-09 18:32, Ian Buckley wrote:
>> Specific to your current problem with building the FPGA. Can you please include the part of the log file related to the error you see please. It's pretty much impossible to help without that information.
>> On Jul 8, 2015, at 10:19 PM, "Faller, Lisa-Marie via USRP-users" <usrp-users at lists.ettus.com> wrote:
>>> By now I managed to build FPGA-master under Ubuntu using Vivado2014.4 (I re-installed Vivado System Design Edition since I understood that the target FPGA -device must be missing).
>>> According to the build under Win7/MinGW: I tried to build the FPGA-maint with ISE 14.7 and managed to setup the PATH accordingly, everything seems to work until x300.v is added as source: it says the x300.v file cannot be found although it is definitely there, any idea on that?
>>> What I want to do finally is ‘abuse’ the USRP-devices (x310) to build a measurement system. To do that, it will be necessary to reduce the code on the FPGA. We want to read baseband signals (up to ~10MHz) from ADCs followed by IQ-demodulation and filtering. On the transmit side we want to generate these carrier signals (so up to ~10MHz). This should be done synchronously for 4 of the x310 devices (at the end). The FPGA-generated carrier signals to be output at the Tx will be used internally for demodulation.
>>> Do you maybe have suggestions on how to go for that concerning FPGA programming?
>>> Thank you and best regards,
>>> Von: Neel Pandeya [mailto:neel.pandeya at ettus.com]
>>> Gesendet: 07 July 2015 20:17
>>> An: Faller, Lisa-Marie
>>> Cc: usrp-users
>>> Betreff: [USRP-users] fpga build win7
>>> Sorry, there was a typo, I meant to say that we have preliminary Vivado support in the master branch.
>>> USRP-users mailing list
>>> USRP-users at lists.ettus.com
> <Screenshot from 2015-07-10 09:38:35.png><build.log>_______________________________________________
> USRP-users mailing list
> USRP-users at lists.ettus.com
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