[USRP-users] WG: fpga build win7
martin.braun at ettus.com
Thu Jul 9 12:09:09 EDT 2015
On 08.07.2015 22:19, Faller, Lisa-Marie via USRP-users wrote:
> What I want to do finally is ‘abuse’ the USRP-devices (x310) to build a
> measurement system. To do that, it will be necessary to reduce the code
> on the FPGA. We want to read baseband signals (up to ~10MHz) from ADCs
> followed by IQ-demodulation and filtering. On the transmit side we want
> to generate these carrier signals (so up to ~10MHz). This should be done
> synchronously for 4 of the x310 devices (at the end). The FPGA-generated
> carrier signals to be output at the Tx will be used internally for
That definitely sounds like a legit use case! Note that at these
bandwidths, you might be able to start working on the host-side before
porting to the FPGA. This might be a simpler way to start. It's also
much simpler to synchronise devices this way.
Also, when you say you need to reduce the code on the FPGA, is that
because you're running out of space, or because the current code does
things you don't care about?
> Do you maybe have suggestions on how to go for that concerning FPGA
Since you're working on the X300 and want to offload computation to the
FPGA, this sounds like an ideal use case for RFNoC. Have you checked out
if that's something for you?
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