[USRP-users] Schematics DDC/DUC chains in x310

Marcus Müller marcus.mueller at ettus.com
Wed Jul 8 12:33:39 EDT 2015


Dear Carlos,

well, if a schematic overview is not enough for your purposes, I think
the only thing sufficient is looking at the source code itself:

looking into https://github.com/EttusResearch/fpga/, consider the
usrp3/top/x300 folder.
Inspecting x300_core.v you'll find that you need to understand radio.v,
https://github.com/EttusResearch/fpga/blob/master/usrp3/lib/radio/radio.v

where the different DSP parts, especially DDC/DUC, are actually
instantiated.

Best regards,
Marcus

On 07/08/2015 03:51 PM, Carlos López-Martínez via USRP-users wrote:
> Dear all,
>
> In the frame of our research activities, we plan to use the x310
> system. Before to actually use them, we plan to do some simulations in
> order to determine the performances we may expect. When confronted to
> the simulation of the whole device, we have found accurate information
> to simulate the daughter-board we are interested into. Nevertheless,
> when addressing the simulation of the digital part, i.e., the
> mother-board, the information is a bit limited. We have found some
> information about the schematics of the DDC/DUC chains implemented
> into the FPGA, but this information is not detailed enough for our
> purposes. I would like to know where we could find the most detailed
> information and/or schematics regarding the DDC/DUC chains implemented
> into the FPGA.
>
> Best regards,
>
> Carlos
>
>
> 	
>
> 	
>
>
>
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