[USRP-users] Schematics DDC/DUC chains in x310
carlos.lopez at tsc.upc.edu
Wed Jul 8 09:51:19 EDT 2015
In the frame of our research activities, we plan to use the x310 system.
Before to actually use them, we plan to do some simulations in order to
determine the performances we may expect. When confronted to the
simulation of the whole device, we have found accurate information to
simulate the daughter-board we are interested into. Nevertheless, when
addressing the simulation of the digital part, i.e., the mother-board,
the information is a bit limited. We have found some information about
the schematics of the DDC/DUC chains implemented into the FPGA, but this
information is not detailed enough for our purposes. I would like to
know where we could find the most detailed information and/or schematics
regarding the DDC/DUC chains implemented into the FPGA.
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