[USRP-users] B210 verilog source code problems
ianb at ionconcepts.com
Tue Jul 7 17:21:23 EDT 2015
I'm going to suggest you start with greatly reduced scope, there's a lot of code you are asking questions about here that is both complicated and unrelated to implementing a simple TX modulator.
The first thing you should do is focus on observing a simple transmit operation running on an unmodified B210 design. Start by instrumenting duc_chain.v using chipscope. This block contains a series of configurable digital filters that allow a signal to be up sampled (interpolated) whilst preserving the original input signal. The input data stream to this block is the raw sample data that is output from GNURadio so by starting here you do not need to understand any of the details of how data is packetized and transported from Host to USRP, but you get to observe *exactly* the same numerical values you see at the sink of your flow graph.
Signals you care about to start with:
clk - Everything in this module and under it runs synchronous this clock. This clock runs at the input sample rate to the AD9361 (which is at a fraction of the Baseband PLL set by UHD). "master_clock_rate" set as an arg to your flow graph controls this clock rate.
rst - Active high reset signal.
sample[31:0] - 32 bit (fractional fixed point) sample data. [31:16] is 16bit signed I data, [15:0] is 16bit signed Q data ( the same ports/data as your UHD: USRP Sink in GNURadio, possibly transformed from floating point to fixed point representation).
run - This control signal is asserted whenever transmit is *active*. Whenever this signal is asserted then the data on the sample bus is valid.
strobe - This control signal is asserted by the DUC in every clock cycle that data from the sample bus is consumed by the DUC.
tx_fe_i/tx_fe_q[WIDTH-1:0] - Output buses with Tx sample data sent to AD9361 (every clk cycle when run is asserted).
This set of signals alone provide enough connectivity to implement a basic BPSK modulator inside the DUC without modifying UHD or GNURadio. Something that is configurable or more sophisticated will require some more signals…but thats the next step.
On Jul 7, 2015, at 10:32 AM, Vitaliy Lazarev via USRP-users <usrp-users at lists.ettus.com> wrote:
> Hi all, again.
> Several months ago I posted a message about some problems in
> understanding verilog code and how it works. Still seeking for help.
> ---------- Forwarded message ----------
> From: Виталий Лазарев <laviol.94 at gmail.com>
> Date: 2015-04-13 15:54 GMT+03:00
> Subject: B210 verilog source code problems
> To: usrp-users at lists.ettus.com
> > Hi All,
> > I'm working on the project by implementing a modulator (e.g.BPSK) in
> > FPGA on board B210.
> > And the more I digging the Verilog code, the more questions I have
> > about how it actually works.
> > Down below I will talk about only a TX chain, because there's no
> > priority to implement an RX chain right now. Anyway, everything has
> > its time and I hope for your help.
> > 1) There's a module gpif2_slave_fifo32 in b200.v file, that gets a
> > tx_tdata and ctrl_tdata lines forward to DSP chain. In this module I
> > found that it works with a tristate buffer model and depending on what
> > information module get (i.e. what's on GPIF_CTL11 and GPIF_CTL12,
> > which are used for fifo address), it will take it to different
> > fifo-modules. Then it splits to tx_tdata and ctrl_tdata. At this point
> > I don't understand the logic of setting these pins (GPIF_CTL11 and
> > 12). Is there any description of transactions into GPIF? Or maybe
> > there's a documentation how to work with this interface?
> > 2) There's a pin, named codec_data_clk_p. This is a Baseband PLL
> > clock, I suppose, that goes from AD9361. I got the full path:
> > DATA_CLK_P -> G11 -> K3 -> IO_L44P_GCLK21_M3A5_3 (codec_data_clk_p).
> > AD datasheet says, that this clock is programmed from 700 MHz to 1400
> > MHz. How should I know, what clock is going from AD right now, when I
> > run my board with .bin and .hex files? Can I change or reconfigure it
> > from somewhere?
> > 3) While I was surfing the source code it was obvious, that tx data
> > goes from tx0 and tx1 buses (inside b200_core.v). It goes up to
> > tx_data1 and tx_data2 and then it goes to catcodec module and to DAC.
> > But when I looked at it with the Chipscope, I didn't see nothing that
> > proves my theory. Tx bus (inside radio_b200.v) consists from run_tx
> > signal and two other buses - tx_idle and tx_fe_q or tx_fe_i (depends
> > on I and Q components). In Chipscope run_tx signal was 0, so data goes
> > only from tx_idle. But I didn't see at least something that was
> > similar to data from tx_tdata (up in b200.v). Honestly, I didn't see
> > nothing on these buses (it was zeroes, or some constant value that
> > didn't change). Here's the question - how data goes from GPIF and
> > tx_tdata bus down to radio_b200 and goes up to tx_data1 and tx_data2?
> > Maybe I did something wrong with Chipscope, but on tx_tdata there's a
> > data, that transmits from GNURadio. I just don't get the full path.
> > Chipscope was running on radio_clk and bus_clk and it didn't change
> > anything.
> > 4) As I said before, while I was chipscoping, run_tx was set to 0. But
> > there a lot of DSP modules inside radio_b200.v, that run from run_tx
> > (e.g. Digital Up Converter, CIC filter, CORDIC-module and so on). It
> > means that these modules are not working right now. But it ruins my
> > understanding of digital up and down converter chains at all! If all
> > these modules aren't used, why they are in the source code? For other
> > board models? Or if I just didn't turn them on, how can I enable them?
> > All of these things are prevent my attempts to implement something in
> > verilog source code.
> > I have a feeling, that I miss some fundamental things. I hope someone
> > will help me with my questions, cause I'm stuck.
> Best regards,
> Vitaliy Lazarev.
> USRP-users mailing list
> USRP-users at lists.ettus.com
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