[USRP-users] XISE project USRP3 B200

Ian Buckley ianb at ionconcepts.com
Tue Jul 7 15:23:53 EDT 2015

You should use the Makefile to directly synthesize new B200 images, this is the only supported build methodology. Review usrp3/top/b200/Makefile.b200.inc and also usrp3/lib/*/Makefile.srcs to see how to add new source files to the project.


On Jul 3, 2015, at 9:47 AM, Ezequiel via USRP-users <usrp-users at lists.ettus.com> wrote:

> Hello , I want to synthesize the project .xise generated by the makefile provided by GitHub ( USRP3 / top / b200 ) to generate a new FPGA bitstream with some more verilog modules created by me , but when I open the project with ISE14.7 i can't synthesize because of errors. How should I proceed to generate the project to make changes?
> Thanks
> Ezequiel
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