[USRP-users] XISE project USRP3 B200
ezebayer at hotmail.com
Fri Jul 3 12:47:08 EDT 2015
Hello , I want to synthesize the project .xise generated by the makefile provided by GitHub ( USRP3 / top / b200 ) to generate a new FPGA bitstream with some more verilog modules created by me , but when I open the project with ISE14.7 i can't synthesize because of errors. How should I proceed to generate the project to make changes?ThanksEzequiel
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