[USRP-users] Missing point of the verilog and C++ file for RFNoC

Martin Braun martin.braun at ettus.com
Wed Jul 1 16:03:36 EDT 2015

On 01.07.2015 06:37, Jason Matusiak via USRP-users wrote:
> I go to gr-howto/build and run: make clean && make
> And that is where I get errors.  In order to get make to work right, I
> have to go into gr-howto/lib/halving_impl.cc and make some changes so
> that it can compile fine.  
> My confusion is that I feel like those changes are then what the block
> is doing, right?  Wouldn't I want the block's task to be done in the
> verilog code?  I am having trouble seeing the mating of RFNoC and the
> OOT modules.

Hey Jason,

ah, I think I see what's tripping you. So, as you can imagine, you need
*some* C++ code to interface RFNoC to GNU Radio. This interface code
only takes care of shuffling the data from the FPGA into the flow graph
and vice versa, as well as exposing register settings to GNU Radio (e.g.
so you can have a slider to control RFNoC blocks).

For the most part, you don't even need to write any C++ code, because
most blocks behave very similarly, and our block 'rfnoc_generic' can be
configured to behave in different ways. In your case, you definitely
won't need to write your own C++ code for GNU Radio.

BUT, you still need to write a grc/<blockname>.xml file so GRC
understands how to integrate your block into a flow graph. This XML file
will instruct GNU Radio to instantiate a 'rfnoc_generic' block, and you
can add your own options to that.

So, in your case, you shouldn't be adding blocks with gr_modtool. Just
instantiate an empty OOT, then copy XML files from gr-ettus (as
examples) to gr-<your_oot_name>/grc/, edit them as appropriate and go ahead.


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