[USRP-users] Missing point of the verilog and C++ file for RFNoC

Jason Matusiak jason at gardettoengineering.com
Wed Jul 1 09:37:12 EDT 2015

> Both work; if you use gr-ettus, it saves you setting up an OOT, but you
> don't 'own' the repo. Starting your own OOT might be more useful and
> versatile, and it's not difficult. Do whatever suits you best!

Sadly, I seem to be missing something (mentally) still.

So I followed the very nice write up previously recommended here:
and it pretty much makes sense (at least conceptually).  

The next step was to combine that knowledge with what I want to do,
create and RFNoC block.  To do that I went into my gr-howto OOT folder
and did:
gr_modtool add -t sync halving
gr_modtool makexml halving

I set it up to use the defaults, be a C++ project, , not have any
parameters, and not have any QA.

I go into gr-howto/grc and edit howto_halving.xml by getting rid of the
two nports tags and changing the in and out types to be complex (instead
of raw).

I go to gr-howto/build and run: make clean && make
And that is where I get errors.  In order to get make to work right, I
have to go into gr-howto/lib/halving_impl.cc and make some changes so
that it can compile fine.  

My confusion is that I feel like those changes are then what the block
is doing, right?  Wouldn't I want the block's task to be done in the
verilog code?  I am having trouble seeing the mating of RFNoC and the
OOT modules.

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