[USRP-users] USRP N210 DDC Sample Data Format

Ian Buckley ianb at ionconcepts.com
Mon Apr 27 12:40:05 EDT 2015


On Apr 27, 2015, at 8:11 AM, Marcus D. Leech via USRP-users <usrp-users at lists.ettus.com> wrote:

> On 04/27/2015 11:08 AM, Patrick DaSilva via USRP-users wrote:
>> Hi,
>> 
>> I've been assuming the data format of the sample out from the DDC on the N210 FPGA is an integer 16Bit Complex (sc16, I(16bits), Q(16bits)). Is this correct?
>> 
>> What does setting the cpu_format and wire_format (fc64, fc32, sc16, sc8)  in the Host UHD driver do if anything to this? Does it change the format in the packet router or VITA RX Chain?
>> 
>> Respectfully,
>> Patrick DaSilva
>> 
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users at lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> The CPU format is entirely on the host side--the USRP knows nothing about it.
> 
> The wire format changes "stuff" in the FPGA just before (as I recall) its injected into the VITA framing.
> 
> 
> 

I've already alluded to this in another response to you, but all DDC and DUC DSP is done using a fractional fixed point representation, and the exact bit widths used vary as appropriate throughout the DDC data path. Samples over the wire to the host always have this weighting i.e the 8bit SC8 value 0x80 and the 16bit SC16 value 0x8000 both represent -1.0. Conversion, as Marcus already said, from the internal varied precision used in the DSP and the format selected for over the wire occurs outside the DUC/DDC (format options on N210 are limited to SC16 and SC8).

-Ian





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