[USRP-users] USRP N210 DDC Sample Data Format
Marcus D. Leech
mleech at ripnet.com
Mon Apr 27 11:11:34 EDT 2015
On 04/27/2015 11:08 AM, Patrick DaSilva via USRP-users wrote:
> I've been assuming the data format of the sample out from the DDC on the N210 FPGA is an integer 16Bit Complex (sc16, I(16bits), Q(16bits)). Is this correct?
> What does setting the cpu_format and wire_format (fc64, fc32, sc16, sc8) in the Host UHD driver do if anything to this? Does it change the format in the packet router or VITA RX Chain?
> Patrick DaSilva
> USRP-users mailing list
> USRP-users at lists.ettus.com
The CPU format is entirely on the host side--the USRP knows nothing
The wire format changes "stuff" in the FPGA just before (as I recall)
its injected into the VITA framing.
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