[USRP-users] B210 verilog source code problems

Виталий Лазарев laviol.94 at gmail.com
Mon Apr 13 08:54:24 EDT 2015

Hi All,

I'm working on the project by implementing a modulator (e.g.BPSK) in
FPGA on board B210.
And the more I digging the Verilog code, the more questions I have
about how it actually works.
Down below I will talk about only a TX chain, because there's no
priority to implement an RX chain right now. Anyway, everything has
its time and I hope for your help.

1) There's a module gpif2_slave_fifo32 in b200.v file, that gets a
tx_tdata and ctrl_tdata lines forward to DSP chain. In this module I
found that it works with a tristate buffer model and depending on what
information module get (i.e. what's on GPIF_CTL11 and GPIF_CTL12,
which are used for fifo address), it will take it to different
fifo-modules. Then it splits to tx_tdata and ctrl_tdata. At this point
I don't understand the logic of setting these pins (GPIF_CTL11 and
12). Is there any description of transactions into GPIF? Or maybe
there's a documentation how to work with this interface?

2) There's a pin, named codec_data_clk_p. This is a Baseband PLL
clock, I suppose, that goes from AD9361. I got the full path:
DATA_CLK_P -> G11 -> K3 -> IO_L44P_GCLK21_M3A5_3 (codec_data_clk_p).
AD datasheet says, that this clock is programmed from 700 MHz to 1400
MHz. How should I know, what clock is going from AD right now, when I
run my board with .bin and .hex files? Can I change or reconfigure it
from somewhere?

3) While I was surfing the source code it was obvious, that tx data
goes from tx0 and tx1 buses (inside b200_core.v). It goes up to
tx_data1 and tx_data2 and then it goes to catcodec module and to DAC.
But when I looked at it with the Chipscope, I didn't see nothing that
proves my theory. Tx bus (inside radio_b200.v) consists from run_tx
signal and two other buses - tx_idle and tx_fe_q or tx_fe_i (depends
on I and Q components). In Chipscope run_tx signal was 0, so data goes
only from tx_idle. But I didn't see at least something that was
similar to data from tx_tdata (up in b200.v). Honestly, I didn't see
nothing on these buses (it was zeroes, or some constant value that
didn't change). Here's the question - how data goes from GPIF and
tx_tdata bus down to radio_b200 and goes up to tx_data1 and tx_data2?
Maybe I did something wrong with Chipscope, but on tx_tdata there's a
data, that transmits from GNURadio. I just don't get the full path.
Chipscope was running on radio_clk and bus_clk and it didn't change

4) As I said before, while I was chipscoping, run_tx was set to 0. But
there a lot of DSP modules inside radio_b200.v, that run from run_tx
(e.g. Digital Up Converter, CIC filter, CORDIC-module and so on). It
means that these modules are not working right now. But it ruins my
understanding of digital up and down converter chains at all! If all
these modules aren't used, why they are in the source code? For other
board models? Or if I just didn't turn them on, how can I enable them?

All of these things are prevent my attempts to implement something in
verilog source code.
I have a feeling, that I miss some fundamental things. I hope someone
will help me with my questions, cause I'm stuck.

Best regards,
Vitaliy Lazarev.

More information about the USRP-users mailing list