[USRP-users] b200 Overflows

Ian Buckley ianb at ionconcepts.com
Mon Sep 29 14:18:29 EDT 2014


Slow(er than needed) host performance can propagate back pressure as far as the FPGA H/W…so it's not (necessarily) indicative of a H/W problem if the H/W flags overflow, just that downstream data consumption is not keeping up.
It may well be possible for UHD to flag Overflow without interaction with the actual USRP under some set of conditions…I just can't speak to that off the cuff, not my area of expertise.


On Sep 29, 2014, at 9:50 AM, Simon Brown <simon at sdr-radio.com> wrote:

> Ah,
>  
> So – is this overrun on the B200 itself or as I assumed inside the UHD.dll’s own buffering? If it’s inside the B200 then it would possibly be firmware?
>  
> Apart from this overrun and something bloody odd errors with USRP1 on USB3 I am, at the moment, a happy camper (I’ll report these errors later).
>  
> Ian – everything helps, I do understand hardware, it’s what people buy. Software on the other hand is assumed to be free…
>  
> Simon Brown G4ELI
> http://v2.sdr-radio.com
>  
> From: Ian Buckley [mailto:ianb at ionconcepts.com]
>  
> Simon, 
> Just to give you the H/W picture, you can visualize Rx data in the B200 as flowing through the following in order:
> DSP->Packetization Logic-> FIFO's
>  
> There actually quite a few FIFO's before the USB interface is reached and they all run (in H/W) much quicker than USB3 throughput.
> Thus data "falls through" and tends to accumulate at the last FIFO(s) where it is rate limited by whatever the USB performance is.
> If the sustained USB throughput (over a significant period of time) can't match the sample rate (rate over the USB wire...DSP output rate) then that chain of FIFO's slowly fills and, when the packetization logic can not add any more samples to the head of the FIFO chain then and overflow error indication is signaled to the host in an error packet (that bypasses the queued sample data).
>  
> Not directly helpful for you I know, but always nice to have the big picture.

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