[USRP-users] Question on max. baseband bandwidth: can we go above 120 MHz on the TX side?

Ian Buckley ianb at ionconcepts.com
Tue Sep 23 13:30:54 EDT 2014

If we assume you are prepared to generate your signal internally to the FPGA you would still practically be limited by the 200Msps rate used to interface to the DAC. There is no practical way to run this interface faster with this schematic design. The DAC internally up samples to 800Msps (makes the anti aliasing filtering easier primarily)

You can also generate a 200Msps complex sample stream on a Host using 10G ethernet but you are on the very edge of what is feasible in current generation computers. 

I think you are approximately correct with the BasicTx limit also, the transformer is limiting, but I don't have a better number for you.


p.s. Marcus, the clock to the DAC is 400MHz but thats because its a QDR interface moving a byte every clock edge.

On Sep 23, 2014, at 9:50 AM, Ruben Merz via USRP-users <usrp-users at lists.ettus.com> wrote:

> Hi list,
> We were discussing with some colleagues today whether to use a USRP (x300 specifically) to generate wideband noise with a basicTX for testing purpose. According to the data-sheet, the x300 can do 120 MHz of RF bandwidth from the host. But when I look into http://www.trondeau.com/storage/grcon14/presentations/Sep16_05_Ettus_Updates.pdf, I see 300+ MHz on slide 9. And if I look further in the spec, the DAC can go up to 800 MS/s.
> Therefore my question: if we were to generate signals directly from the FPGA; would it be feasible to generate 400 MHz wide signals (I understand that the basicTX is limited to 250 MHz though)? Where would be the limitation?
> Thanks for any comment
> Ruben
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