[USRP-users] External Tx/Rx switch control with B210
ianb at ionconcepts.com
Tue Sep 9 15:42:58 EDT 2014
By happy coincidence I started work on this long overdue project last Friday. You'll note that Ettus has just started shipping a new version of B2x0 that includes a new 10 pin 0.1" header (J504) that will provide 8 bits of GPIO functionality with the same API as X3x0's front panel GPIO. (http://files.ettus.com/manual/page_gpio_api.html)
As a freebie I'm also throwing in a standard FPGA build option that reuses the 2 UART signal pins on J400 present on all B2x0 versions as 2 extra GPIO bits.
BTW, new GPIO header is 3.3V, UART header is 1.8V.
You could indeed if you wish easily grab the signal that drives the LED's within the FPGA and replicate it on the UART header with simple Verilog changes.
On Sep 9, 2014, at 11:35 AM, "Nowlan, Sean via USRP-users" <usrp-users at lists.ettus.com> wrote:
> I’ve seen a few threads discussing various options for bringing out a signal to control an external Tx/Rx switch with a B210. A couple suggestions were to use a debug pin through the MICTOR connector or an unused debug UART pin. Both seemed to require FPGA modifications. Has anybody made headway with this? There was also talk of UHD firmware binaries including something like this as a feature.
> If there’s nothing like this supported out-of-the-box, we can make some FPGA changes. What I’d like to know is:
> 1) What changes would have to be made? Is it as simple as toggling an output pin based on a TX/RX/IDLE signal in the FPGA code (I think this logic is called “ATR”)?
> 2) What kind of delay can we expect between when this signal is active and when RF is actually being modulated over the air? If I understand correctly, this signal is driven by whether samples are present in the TX buffer. It sounds like we would have to account for delays due to the DSP chain and RF frontend. Is this understanding correct? We could probably measure and calibrate that out. However, what happens if we are using timed bursts? Does the TX signal only go active once the scheduled time is reached?
> 3) What voltage level is brought out to the UART pins? Is it 3.3V?
> Aside from FPGA, can we pull this signal from tx_enable that is driving the status LEDs?
> Best regards,
> Sean Nowlan
> USRP-users mailing list
> USRP-users at lists.ettus.com
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