[USRP-users] User Settings Bus on X3x0

Ashish Chaudhari ashish.chaudhari at ettus.com
Mon Sep 8 12:53:34 EDT 2014


Hi Hrishikesh,

We are planning to integrate the N2x0 style user settings (or something
better!) into the B200 and X300 but that is currently not scheduled for the
short term. Until then, as you mentioned, you can instantiate more settings
modules in the radio. Getting access to the new registers in UHD should not
require any special work in UHD other than implementing code to access
them. Once you HDL has the new settings, you can access them using the
radio_ctrl_core_3000 [1]. There are two instances of this object (one per
radio) and you can use poke32 to exercise the settings.

[1]
https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/x300/x300_impl.cpp#L892

*Ashish Chaudhari* | Senior Software Engineer | High Frequency Measurements
- RF
Ettus Research, *A National Instruments Company*

On Fri, Sep 5, 2014 at 4:24 PM, Hrishikesh Shelar via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Makes sense. Instead of using the user settings logic would it be possible
> to just to instantiate more settings reg modules having addresses higher
> than the last ones used by the USRP (which I think is SR_TX_FRONT = 216).
> So lets say I started at 230? Also is there any easy way to set these
> registers within UHD or will I have to add a custom block of code in
> x300_impl.cpp.
>
> Thanks,
> Hrishi
>
>
> On Fri, Sep 5, 2014 at 11:41 AM, Ian Buckley <ianb at ionconcepts.com> wrote:
>
>> I suspect the answer is neither in your case. The X310 has three separate
>> settings buses, one in each radio, and the one you highlighted thats is
>> multi-master and lives in the ZPU/core clock domain.
>>
>> X310 differs from N210 in that the Radio's run asynchronously from much
>> of the packet processing logic in the core.
>>
>> The settings busses in the radios are exclusively mastered through direct
>> UDP packets using the CHDR protocol (this having superseded VRT for USRP3
>> generation products).
>>
>> If your custom logic runs at the radio clock rate, within the radio
>> hierarchy, then logically your new settings bus registers should be placed
>> on the settings bus within the (appropriate) radio.
>>
>> -Ian
>>
>>
>> On Sep 5, 2014, at 10:58 AM, Hrishikesh Shelar via USRP-users <
>> usrp-users at lists.ettus.com> wrote:
>>
>> > Hey all,
>> >
>> > I want to tag on the user settings module from the N2x0 series into the
>> X310 fpga code. I see that there are two paths for the SR bus; one through
>> the ZPU wishbone and one through direct UDP packets using VRT control, is
>> this right? Which bus would be the best to use? I need to access my custom
>> blocks in the DDC and DUC chains.
>> >
>> > Thanks,
>> > Hrishikesh Shelar
>> > _______________________________________________
>> > USRP-users mailing list
>> > USRP-users at lists.ettus.com
>> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
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>
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