[USRP-users] User Settings Bus on X3x0

Hrishikesh Shelar hshelar at umich.edu
Fri Sep 5 19:24:40 EDT 2014

Makes sense. Instead of using the user settings logic would it be possible
to just to instantiate more settings reg modules having addresses higher
than the last ones used by the USRP (which I think is SR_TX_FRONT = 216).
So lets say I started at 230? Also is there any easy way to set these
registers within UHD or will I have to add a custom block of code in


On Fri, Sep 5, 2014 at 11:41 AM, Ian Buckley <ianb at ionconcepts.com> wrote:

> I suspect the answer is neither in your case. The X310 has three separate
> settings buses, one in each radio, and the one you highlighted thats is
> multi-master and lives in the ZPU/core clock domain.
> X310 differs from N210 in that the Radio's run asynchronously from much of
> the packet processing logic in the core.
> The settings busses in the radios are exclusively mastered through direct
> UDP packets using the CHDR protocol (this having superseded VRT for USRP3
> generation products).
> If your custom logic runs at the radio clock rate, within the radio
> hierarchy, then logically your new settings bus registers should be placed
> on the settings bus within the (appropriate) radio.
> -Ian
> On Sep 5, 2014, at 10:58 AM, Hrishikesh Shelar via USRP-users <
> usrp-users at lists.ettus.com> wrote:
> > Hey all,
> >
> > I want to tag on the user settings module from the N2x0 series into the
> X310 fpga code. I see that there are two paths for the SR bus; one through
> the ZPU wishbone and one through direct UDP packets using VRT control, is
> this right? Which bus would be the best to use? I need to access my custom
> blocks in the DDC and DUC chains.
> >
> > Thanks,
> > Hrishikesh Shelar
> > _______________________________________________
> > USRP-users mailing list
> > USRP-users at lists.ettus.com
> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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