[USRP-users] Spurious signals from packet loss?? / why Integer-N tuning

Radio User radiogeek381 at gmail.com
Fri Oct 31 20:03:24 EDT 2014


Daniele,

The mode=integer_n switch switches the front-end LO in the WBX, and some
other daughter cards from the default "fractional-N" mode to "integer-N"
mode.

Here's what that means:

A PLL based synthesizer (there are other kinds of synthesizer, but the
front-end
LO uses a PLL.)  takes an input reference frequency Fref and multiplies it
by
some factor to get an output frequency Fout.

This is done by building a feedback loop that controls an oscillator.
The oscillator output gets divided down and compared to the reference
frequency.
If the output freq is too low, the loop pushes the oscillator up, too high
and
we push the oscillator down.  (This is a digest of approximately a
bazillion
pages on the fine art of PLL design.  Got a year or two with nothing to do
-- start
with Gardner's "Phaselock Techniques.")

An integer-N synthesizer takes an input reference frequency (say 1MHz) and
multiplies it up to get the output frequency, like this

Fout = Fref * N

by using a simple integer divider (think of a counter that resets to zero
every
time it gets to N-1) in the feedback loop.

If you were to do that in general, you get a wide channel spacing -- 1MHz
in this
case.  The obvious dodge for this problem is to divide the reference
frequency down
by some fixed factor, like this

Fout = (Fref / R) * N

For instance, if Fref was 1MHz and R was 100, we could build a synthesizer
with a
10 kHz channel spacing.  If the target frequency range was something like
145 to 148
MHz, that would mean that N would take the range 14500 to 14800 -- that's
an 18 bit
counter.  Not out of the question, but such an oscillator would probably
not look
very clean -- we injected a lot of switching-induced phase noise into the
reference
oscillator (dividers inject some noise into their outputs due to jitter in
the "decision point"
for their logic inputs, -- very long story) and then multiplied it back up
14500 times to add
another 40dB to the close-in-phase-noise.

(USRP sophisticates -- please forgive the omissions here about running the
loop VCO
at 2,4,8,16,32 x the actual output freq -- this is complicated enough as it
stands.  If
the simplification offends, write your own explanation...)

So back when dinosaurs roamed the earth, (at least prior to 1987) someone
had the
idea to build a phase-locked-loop configuration that provided this:

Fout = (Fref/R) * (N + K / M)

This is a "fractional-N" synthesizer.  The actual implementation can
confuse folks, but
the premise is that the divider in the feedback loop divides by f(N) for
some of the
time and f(N) + A for the rest of the time.  The divider switches back and
forth
between the two divide ratios based on the ratio K/M and A.

You can imagine that if M was, say, 1000 and R was 1 and Fref was 1 MHz,
we could build a synthesizer like this that did 1kHz steps.  And N would
only
have to cover the range 145 to 147.  And since R=1 we didn't inject the ref
divider
noise.  And since the multiplier was 145, we injected 20dB of phase noise
rather than 40dB.

Not a bad tradeoff -- why wouldn't we do that everywhere?

And so, for the most part we do.

The downside however, is that wiggling between f(N) and f(N)+A.  It happens
at a rate that is related to M and is not random -- it has a frequency
spectrum
that has spikes in it at intervals something like Fref/(M*R).

So, if you are really interested in looking at very weak signals, that are
near
the noise floor of the system, these spikes (yet another source of "spurs"
or
"birdies" in RF-people slang) can get pretty annoying.  (On a radio that
shows
a waterfall display, they show up as stripes. Worse, they are like little
shadow
local oscillators that can beat against signals pretty far away from the
signal
that you care about <emphasis>and frequency-shift them over top of your
desired signal</emphasis>.  That's really bad for those of us looking for
tiny signals among slightly larger signals.)

Since the A/D part of the N200 is pretty wide (the sample rate is high),
we can take advantage of that by using the digital down converter (DDC)
in the FPGA to do all the fine tuning steps.  That removes the need for
small
(fractional-N) tuning steps in some weak-signal receiver applications.

It can complicate tuning though.  The DDC offset parameter to set_rx_freq
doesn't always do what you (or maybe what I) would expect. (Ettus guys: I'm
working on a reproducer for this one.)  Also the integer N steps get larger
as the frequency goes up.  (This is a consequence of the post-VCO divider
in the synthesizers.)

But if you have a taste for RF adventure, and an unpleasant tendency to
fret and worry about the most minute details, integer-N tuning may be
just the thing for you. (It is for me!)  It is the default tuning mechanism
for SoDaRadio ( http://sodaradio.sourceforge.net/Site/SoDaRadio.html )


radiogeek
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