[USRP-users] Toggling GPIO's from USRP FPGA

Ian Buckley ianb at ionconcepts.com
Wed Oct 29 19:03:24 EDT 2014


Anum,
I think at this stage we are going to need a picture of what you are seeing on the oscilloscope together with a description of how you have the oscilloscope connected to make further progress.

-Ian

On Oct 28, 2014, at 9:52 PM, Anum Sheraz <anumsheraz1 at hotmail.com> wrote:

> Appreciate your quick response Lan,
> 
> Well i considered your point of toggling at high rate. I am using dsp_clock (one that the GPIO_atr module is using)and i am dividing this clock further down to lower rate. but the issue is,
> 
> While i was testing the pins 10,11,12,13,14,15 (which i am toggling), this strange fix pattern of sin wave is observed not only in these pins but also on other pins (i.e. io_rx aswell). I also have another USRP kit (with default FPGA firmware), and i observed the output of io_tx pins, the same sine wave pattern was coming on those pins aswell. What can be the reason for this ? 
> 
> There is a note written on GDB schematic "NOTE: any combination with ’−’ is not possible with gpio control " and also there a table shown above this note aswell. what does this table represent ? 
> 
> and thanks to you for saving my USRP, actually i didn't noticed that the 14 and 15th pins are being used by antenna select and attenuation purpose. let me change that bus from 13:8 now. 
> 
> -Anum
> 
> Subject: Re: [USRP-users] Toggling GPIO's from USRP FPGA
> From: ianb at ionconcepts.com
> Date: Mon, 27 Oct 2014 23:13:15 -0700
> CC: usrp-users at lists.ettus.com
> To: anumsheraz1 at hotmail.com
> 
> OK first off…STOP!
> You can not reuse GPIO that are already being used by a daughter board, both io_tx[14] and io_tx[15] are used by the WBX and are not available for your free use.
> Re-purposing GPIO pins that are already in use without careful consideration risks effects on the spectrum between: unexplained behavior, through board destruction.
> If you need a bus of 6 bits then, as shown on page 5 of the WBX schematic bits [13:8] of io_tx are UNUSED. Leave bits of GPIO used by the daughter board connected to the GPIO_ATR modules.
> (Note also that there is an error on page4 of the current WBX schematic - io_rx[5] is unused, io_rx[15] controls RX1/RX2 selection.)
> 
> Now if what you mean by:
> but i see a strange fix pattern of sin wave.
> 
> is that you examine a single bit of GPIO and do not see clean digital edges but instead see large rise and fall times w.r.t the expected toggle frequency then it's likely you are toggling that signal too fast…remember these are not signal traces optimized for the transfer of high speed bussed data.
> What clock is driving your counter? Does the MSB of your counter look better than the LSB?
> The Mictor connector on the N210 motherboard is a far better choice if you need to add a user designed high speed data interface to N210.
> 
> -Ian
> 
> 
> On Oct 27, 2014, at 9:47 PM, Anum Sheraz via USRP-users <usrp-users at lists.ettus.com> wrote:
> 
> Hi there,
> 
> I have configured a new custom block inside the FPGA of USRP N210. This block contains a simple 6 bit up Counter. and i've connected the these 6bits output to the io_tx[15:10] line on the FPGA. instead of io_tx[15:0] going directaly to the GPIO_atr module, now its 6 bits [15:10] are connected to the counter's output and the remaining 10 bits are not used. 
> 
> I've tested the output of these Pins on oscilloscope, but i see a strange fix pattern of sin wave. i am expecting to see a square pulse.
> 
> My daughter board is WBX and a Simple Granddaughterboard , GPIO pins that are available are brought out to J15 on the GDB for WBX. I was reading the schematic of this GDB and i found out some conditions of using these GPIO. do i need to keep the io_rx[15]=0 ?
> 
> its all going above my head. Does anyone has any idea about this ? 
> 
> Any help will be highly appreciated.
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