[USRP-users] A question about CBX daughterboard tuning time
marcus.mueller at ettus.com
Wed Oct 29 16:02:18 EDT 2014
"tuning time" can be understood in two ways:
1. Latency, which then is t_command_latency + t_tuning_stabilization
2. t_tuning_stabilization, the time between the start of tuning and the
point where samples are as reliable as before.
You can hide latency completely by using timed commands, please see the
UHD manual for further information.
Tuning happens in two ways: The LO is retuned, and the digital frequency
shifting is set up in the FPGA DSP chain; this allows for
arbitrary center frequencies.
Digital tuning alone, as can be specified by tuning using tune_request_t
objects, happens very fast, sub-2ms, I'd say.
Analog tuning of the SBX, if I remember correctly, happens in about 5ms,
so the total tuning time from command time to stable signals would be
There is another big contributor to Tuning Time: There is a feature
(which you can disable via multi_usrp::set_?x_dc_offset) to eliminate DC
offset, which sets up a high pass IIR filter in the FPGA, which, on the
USRP2 architecture, exhibits around 50-60ms measurable impulse response,
that you'll see upon tuning. On the X300, that should be faster.
On 29.10.2014 09:15, Nahla Kamel Fahmy via USRP-users wrote:
> Could you please tell me what the tuning time for CBX daughterboard (for
> frequency hopping) is?
> Thanks and best regards,
> USRP-users mailing list
> USRP-users at lists.ettus.com
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