[USRP-users] documented memory-map and streaming interfaces

Martin Braun martin.braun at ettus.com
Tue Oct 28 06:44:21 EDT 2014


On 10/22/2014 07:02 PM, David Watt via USRP-users wrote:
> We need to run the Ettus X310 in a mode that’s quite a bit different
> than the I&Q samples to & from software mode. Our mode can’t really be
> implemented by putting a DSP block in either the Tx or Rx streaming paths.
> 
> Is there a more general way to interface between software and the FPGA
> internals? There’s a wishbone bus inside – is there a C API that can
> read/write from this directly without all the other UHD layers? Is there
> an API for uploading a stream data packet and a documented timing
> protocol on the FPGA side for how it would ingress into the FPGA? And
> vice versa for packetizing a data stream from FPGA to software? Any
> pointers are appreciated.

Hey David,

other than what we have in UHD, there's no API that we've written to
access the device.

I'd be curious what exactly it is you want to do -- maybe it *can* be
done with our existing streaming API.

Cheers,
Martin





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