[USRP-users] documented memory-map and streaming interfaces
david.watt at sri.com
Wed Oct 22 13:02:13 EDT 2014
We need to run the Ettus X310 in a mode that's quite a bit different than the I&Q samples to & from software mode. Our mode can't really be implemented by putting a DSP block in either the Tx or Rx streaming paths.
Is there a more general way to interface between software and the FPGA internals? There's a wishbone bus inside - is there a C API that can read/write from this directly without all the other UHD layers? Is there an API for uploading a stream data packet and a documented timing protocol on the FPGA side for how it would ingress into the FPGA? And vice versa for packetizing a data stream from FPGA to software? Any pointers are appreciated.
Thank you, David Watt
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