[USRP-users] Keep transmitted signal in USRP to overcome the limited host sample rate of E100/E110
srisooksai at gmail.com
Tue Oct 21 20:49:52 EDT 2014
Thank you for your answer.
In my case, I want to sent the periodic signal. It means that I just want
to keep one set of signal in FPGA and send it out repeatedly.
As my calculation, it takes < 100 Kbits. That's why I think that it can be
stored in FPGA of E100/E110.
On Tue, Oct 21, 2014 at 8:11 PM, Marcus Müller <usrp-users at lists.ettus.com>
> the FPGA is not a storage device, and even if you could use all the block
> RAM on the FPGA and add some more memory by using logic cells, you won't
> store /much/ on the moderately sized E100 FPGA or even on the E110's one.
> So, you'd be limited to short bursts of TX samples.
> The question whether something is "simple work" heavily depends on the
> experience of the one doing that work. Since you ask, I assume you're not
> very experienced doing FPGA development; as that seems to exhibit a rather
> steep learning curve, I'm afraid the answer is "it's not simple".
> On 17.10.2014 09:38, Jack via USRP-users wrote:
> Hi -
> As you know, embedded series, E100/E110, has the limited host sample rate,
> just only 4MS/s. But I want to send bigger signal bandwidth (ex. 20Mhz).
> My idea to overcome this issue is to keep the transmitted signal inside
> FPGA. But I have not started to work on this yet. Have anyone tried to do
> so? Could you share your experience? Is it possible? Simple work? or
> Complicated work?
> Best Regards,
> USRP-users mailing listUSRP-users at lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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