[USRP-users] Keep transmitted signal in USRP to overcome the limited host sample rate of E100/E110

Jack srisooksai at gmail.com
Fri Oct 17 03:38:06 EDT 2014


Hi -

As you know, embedded series,  E100/E110, has the limited host sample rate,
just only 4MS/s. But I want to send bigger signal bandwidth (ex. 20Mhz).

My idea to overcome this issue is to keep the transmitted signal inside
FPGA. But I have not started to work on this yet. Have anyone tried to do
so? Could you share your experience? Is it possible? Simple work? or
Complicated work?

Best Regards,
Jack
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