[USRP-users] B210 FPGA/FW Issue

Ralph A. Schmid, dk5ras ralph at schmid.xxx
Thu Oct 16 13:00:25 EDT 2014


Well, I _love_ the design of the bladeRF with its SPI flash for both images.


 

Ralph.

 

 

From: USRP-users [mailto:usrp-users-bounces at lists.ettus.com] On Behalf Of
Ian Buckley via USRP-users
Sent: Tuesday, October 14, 2014 11:32 PM
To: hossein talaiee
Cc: usrp-users at lists.ettus.com
Subject: Re: [USRP-users] B210 FPGA/FW Issue

 

Nope. There is non no-volatile memory on the board to store the FPGA
configuration.

This in fact makes the design much easier since handling the update and
fail-safe of stored images is a non-trivial problem.

-Ian

 

On Oct 14, 2014, at 2:19 PM, hossein talaiee via USRP-users
<usrp-users at lists.ettus.com> wrote:





Why ?

Can't be permanently programmed on board?

 

On Wed, Oct 15, 2014 at 12:21 AM, Marcus Müller <usrp-users at lists.ettus.com>
wrote:

Hi Hossein,

these images have to be loaded everytime you reset your device, ie. whenever
you plug it into power; it's not a one-time procedure.

Greetings,
Marcus

 

On 14.10.2014 22:39, hossein talaiee via USRP-users wrote:

Hi
 
I have e B210 board with spec:
 
revision: 4
product: 2
FW Version: 4.0
FPGA Version: 3.0
 
 
Each time I want to run examples of UHD like benchmark it start to load
FPGA image and sometimes fw too!
 
Why this happen? Isn't it a one time procedure ?
 





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