[USRP-users] Confused about the definition of naming pins in FPGA code

Isen I-Chun Chao chao926 at gmail.com
Sat Oct 4 20:36:31 EDT 2014


Thanks Ashish,
It does help me figure it out.


*Best Regards,Isen I-Chun Chao*

On Fri, Oct 3, 2014 at 7:33 PM, Ashish Chaudhari <ashish.chaudhari at ettus.com
> wrote:

> Hi Isen,
>
> The signals that you are looking at are a part of the AMBA AXI4-Stream
> Interface [1] that is used widely in the X3x0 design. Several signals have
> to come together to form a "stream" and they are not in the same direction.
> For instance, if you have an AXI stream going from A to B then you would
> have the following signals:
> - tdata: Data asserted by A for consumption by B
> - tvalid: If asserted then the data on the "tdata" bus is valid
> - tlast: If asserted then this is the last word in the burst/packet/frame
> - tready: If asserted then B is ready to consume more data from A
>
> tdata, tvalid and tlast go from A->B and tready goes from B->A. Data is
> only transferred when tvalid and tready are both asserted. The "i_" and
> "o_" prefixes on the data just indicate the direction of the stream where
> 'i' means input and 'o' means output. For example, i_tvalid refers to the
> tvalid signal for the input stream for a particular block, and it should be
> an "input" port. Similarly o_tready refers to the tready signal for the
> output stream which is also an input port.
>
> Hope that helps clear things up.
>
> [1]
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0051a/index.html
>
> *Ashish Chaudhari* | Senior Software Engineer | High Frequency
> Measurements - RF
> Ettus Research, *A National Instruments Company*
> ashish.chaudhari at ettus.com
>
> On Fri, Oct 3, 2014 at 12:27 PM, Isen I-Chun Chao via USRP-users <
> usrp-users at lists.ettus.com> wrote:
>
>> Hi
>> I am digging into the '*radio.v*' of X310 FPGA code. When I traced it
>> into module '*axi_fifo_short*', I am so confused about the definition of
>> "*i_tvalid*", "*o_tready*", which are inputs, and "*i_tready*", "
>> *o_tvalid*", which are outputs. This four signals are used throughout
>> radio module.
>>
>>
>> Also, if the range of the register '*a*' is from 0 to 30, is that mean
>> this FIFO (*axi_fifo_short*) is only 31 length?
>>
>> Thanks.
>>
>>
>>
>> *Best Regards,Isen I-Chun Chao*
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users at lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>
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