[USRP-users] Xilinx ISE Preprocessor Statements

Ian Buckley ianb at ionconcepts.com
Thu Dec 18 15:41:36 EST 2014


Jeremy,
The PROJECT_ONLY option has been added since I last worked on that makefile but I can give you some pointers here that should allow you to solve your problem with less work than you envisage.

First of all, ISE's Verilog parser interprets pre-processor directives correctly, what is happening here is something different.
When you run the Makefile normally the ISE property "Verilog Macros" is set to "SPARTAN6=1 B200_CAN_HAZ_R1=1 " as ISE is invoked and this cause the Verilog parser to behave as if it had already read lines defining these pre-processor definitions.

When you run with the PROJECT_ONLY=1 option, then an XML record cottoning this property is generated:
   <property xil_pn:name="Verilog Macros" xil_pn:value="SPARTAN6=1 B200_CAN_HAZ_R1=1 " xil_pn:valueState="non-default"/>
 
…but for reasons unknown it seems that when you some  time later invoke ISE it isn't applied in the same way as when its passed via the command line. This might for example be and ordering problem…that property has to be in place before the verilog file that is sensitive to it (b200_core.v) is read. I'm afraid there will be little to no support for the internal quirks of ISE (and it has many!)…it's not used at Ettus in an interactive way, only called as a batch processor form Make.

Your simplest course of action is I think to edit b200_core.v and add as the first line:
`define B200_CAN_HAZ_R1

I have no idea where/when in the code `SPARTAN6 was expected to be defined…that may be completely obsolete…all the current code uses the definition of DEVICE to make FPGA dependent code decisions.

I do encourage you to try to work in a batch oriented methodology though, its a better way to do things in a quality way.

-Ian

On Dec 18, 2014, at 11:05 AM, Jeremy Hershberger via USRP-users <usrp-users at lists.ettus.com> wrote:

> When using the B210 makefile with the "PROJECT_ONLY=1" option, the generated Xilinx ISE Project fails to instantiate radio1.
> 
> If I examine b200_core.v, I notice that there is an "ifdef B200_CAN_HAZ_R1" statement which is supposed to allow instantiation of radio1 but fails to do so.  The B210 makefile passes B200_CAN_HAZ_R1=1 into project creation, but yet radio1 remains uninstantiated.
> 
> Are preprocessor statements, like ifdef, recognized by ISE?  Is there some way to hard-code variables from the makefile into my ISE project, or am I forced to search through all of the verilog files deleting the ifdef statements?
> 
> -Jeremy
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