[USRP-users] LFTX output amplitude (Michael Rahaim)

Michael Rahaim mrahaim at bu.edu
Fri Dec 12 09:50:19 EST 2014

Hi Ian,

Thanks for the reply. I'm not extremely familiar with the details of the
hardware implementation within the USRP - Am I correct in saying that the
CORDIC processor implements the interpolation on the FPGA within the USRP
motherboard and the LFTX implements the complex multiplication of the up
sampled signal with the carrier?

In that case, the "attenuated" signal that I'm seeing is in fact due to the
interpolation and depends on the phase value when I set the carrier back to
0. This seems to imply that the LFTX is in fact passing the I and Q
components through when the carrier is set to 0; but my the real valued
signal that was passed to the USRP has been transformed to a complex value
that is dependent on the value of PHASE before it reaches the LFTX. This
makes sense since I see the signal split across the LFTX outputs (A and B)
which I'm assuming are the I and Q components of the carrier multiplied
complex signal. (Please feel free to send me a virtual slap if I'm saying
something nonsensical).

Regarding my reason for asking, I'm working with an IM/DD optical wireless
setup that can either utilize real valued baseband techniques or passband
techniques at a low frequency carrier. I'd like to be able to switch
between techniques dynamically, but I never know what the amplitude of my
signal will be when I go back to the baseband modulation. I could stop and
restart the flow graph whenever I switch, but I was curious if there was a
way to reinitialize on the fly.

Thanks again for your help,


On Fri, Dec 12, 2014 at 2:42 AM, Ian Buckley <ianb at ionconcepts.com> wrote:

> OK, time for a DSP recap I think. Whilst it makes life easier when we draw
> a system diagram and get to add a single block labelled CORDIC, I think we
> run the risk of forgetting what function it's actually performing.
> Referring to a nice old fashioned pencil diagram:
> http://www.ionconcepts.com/files/CORDIC.jpg
> In the context of a DDC/DUC we are using a CORDIC algorithm processor to
> replace a logical DDS and complex mixer, which in practical terms amounts
> to a PHASE accumulator that endlessly counts 0->2*Pi then wraps at a rate
> determined by the PHASE_INCrementor.
> That PHASE value is the input to lookup tables for SIN and COS functions
> thus synthesizing a complex sinusoid digitally.
> To effect a frequency shift of a complex signal we mix that DDS output
> with the input signal, which in terms of digital operations means we are
> doing a complex multiply of the SIN/COS values with the complex components
> of the input signal.
> So when PHASE = 0 and PHASE_INC = 0, IOUT = IIN and QOUT= QIN. Now whilst
> streaming if we retune the CORDIC and introduce a frequency translation,
> PHASE_INC != 0 and PHASE increments by PHASE_INC every clock cycle. We then
> later retune the CORDIC so that no frequency translation is introduced and
> now PHASE_INC = 0 again. However PHASE is left at an unknown and likely
> non-zero value which means our complex input signal is still rotated around
> the unit-circle. to produce the output signal:
> Now, referring back to Michaels original post he has a flow graph that
> introduces a real only signal into the I channel and leaves the Q channel
> at 0…I think the problem becomes apparent. Now if the input signal is
> instead complex valued then the issue goes away.
> When a new streamer is set up, (TX or RX) PHASE will be initialized to 0,
> and PHASE_INC will have been step-up by UHD to satisfy the current tuning
> request. The only way to return PHASE to zero predictably is to restart the
> streamer.
> -Ian
> On Dec 11, 2014, at 7:53 AM, Michael Rahaim via USRP-users <
> usrp-users at lists.ettus.com> wrote:
> Thanks Lou. I think I get what you're saying, but the end result seems to
> end up as a channel gain as opposed to a DC offset. For example, if I set
> my signal so that it initializes to a sine wave with peak to peak amplitude
> of 1V, after turning the carrier on and off it might end up having a pk-pk
> amplitude of 0.5V or 0.2V or 0.8V.
> Is there a way to reset via software such that the accumulator gets set
> back to 0?
> Thanks again,
> -Mike
> On Thu, Dec 11, 2014 at 9:08 AM, Louis Brown <rfengr00 at me.com> wrote:
>> Ok what you are describing is the phase accumulator halting to a non zero
>> state when you tune the oscillator back to 0 Hz.  Try generating a very low
>> frequency sine wave (a few Hz) and you see what I mean when you tune it
>> away from 0 Hz and then return it.  When you start you flow with a 0 Hz
>> source, the accumulator is initialized to zero, then it starts accumulating
>> when you tune it to some frequency.  Return it to 0 Hz and it stops at a
>> non-zero phase, which is equivalent to a DC offset.  I'm sure this is the
>> way it is supposed to work, and is what I have observed before.
>> Lou
>> On Dec 11, 2014, at 07:21, Michael Rahaim <mrahaim at bu.edu> wrote:
>> Hi Lou,
>> I have the output of the LFTX connected to a scope. I'm not using the
>> LFRX in the test loop.
>> Best,
>> -Mike
>> On Wed, Dec 10, 2014 at 7:44 PM, Louis Brown via USRP-users <
>> usrp-users at lists.ettus.com> wrote:
>>> How are you measuring the LFTX output?  With additional test equipment
>>> or looping it back into the LFRX?
>>> Lou
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>>> USRP-users at lists.ettus.com
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