[USRP-users] RFNoC -- Making FPGA design easy from GNU Radio

Matt Ettus matt at ettus.com
Tue Dec 9 16:36:06 EST 2014


We have thought about that.  The reason we haven't done it so far is that
it is a big change to the expected behavior, and forces the use of RFNoC in
all apps.  We are considering it along with other future changes to the
radio block, but in the mean time you can effectively get that same
behavior by making DDC RFNoC blocks, and using the main one with a
decimation/interpolation factor of 1.

Matt

On Tue, Dec 9, 2014 at 1:09 PM, Jacob Gilbert via USRP-users <
usrp-users at lists.ettus.com> wrote:

> Martin,
>
> Thank you for the information - this gives me a rough idea of what I was
> looking for.
>
> With regard to my question #2, has there been any thought to separating
> radio and DDC chains logically in the FPGA to enable the use case
> discussed? It seems like something that would be useful, particularly given
> the newfound FPGA flexibility.
>
> Jacob
>
> On Mon, Dec 8, 2014 at 2:16 PM, Martin Braun via USRP-users <
> usrp-users at lists.ettus.com> wrote:
>
>> Jacob,
>>
>> I hope you don't mind if I give you some of the answers for now:
>>
>> On 12/08/2014 04:13 PM, Jacob Gilbert via USRP-users wrote:
>> > Matt,
>> >
>> > Congratulations on the release of this - this is very exciting! I have a
>> > few questions:
>> >
>> > 1) This looks targeted at the X3xx series for now; I understand the new
>> > E310 SDR will have RFNoC support also - is there a timeline for this?
>>
>> Development is pretty far. It's already possible to do some RFNoC tasks,
>> we're still ironing out some kinks though.
>>
>> > 2) If I understand the wiki, the current RFNoC FPGA build has a few
>> > example signal processing FPGA blocks (FIR, FFT, window, add/sub) and
>> > several utility blocks (null source/sink, loopback) as well as ‘radio’
>> > blocks. How does the standard USRP FPGA functionality (DDC/DUC chains,
>> > timed commands, etc) fit into this? Is all of that packaged in the
>> > ‘radio’ block or can, for example, a radio block be programmatically
>> > connected to multiple DDC chains that are independently controlled?
>>
>> Currently, all the radio stuff is part of the radio block. If you want
>> full bandwidth, you can simply set the decimation to 1 and process the
>> sample stream in the next block (which could have its own DDC stage, if
>> that's what you need).
>>
>> > 3) What is the FPGA resource utilization of the example X3xx images? Is
>> > there an idea if the same functionality would fit on the E310 FPGA?
>>
>> On X300, it's pretty full. We currently distribute the same example
>> image for X300 and X310, so the latter has free space accordingly.
>>
>> E310 FPGA space is much smaller, though. We can't fit all the blocks
>> from the X-Series' image in there. It'll be a while before we know for
>> sure how much people can get in there (it also depends on one's FPGA
>> skills, of course).
>> However, we are using the identical blocks on both devices (X and E), so
>> it's not like you have to re-write them for E310 or anything. It's just
>> a subset of what we're currently distributing for X-Series.
>>
>> Cheers,
>> Martin
>>
>>
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>
>
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