[USRP-users] N210 DSP Group delay

Ian Buckley ianb at ionconcepts.com
Mon Dec 8 12:30:47 EST 2014


N200 and N210 would be identical. I don't have a gut feel for the analog with a high degree of confidence but I assume its a relatively small number w.r.t the digital component. Calibration would be the way forward for sure with that. I should probably double check the FIR pipeline design in TX to be sure it really is largely the same. As you can see at higher decimations/interpolations HB2 starts to dominate the delay pretty quickly.

On Dec 8, 2014, at 8:22 AM, "Nowlan, Sean" <Sean.Nowlan at gtri.gatech.edu> wrote:

> Thanks, this is great info. So on the transmit side, packets are deframed and their timestamp corresponds to the 10ns clock cycle when the DSP chain begins processing samples? Then, hypothetically, if I timestamp a packet for (t_wall - t_group - t_analog), where t_group is given by your formula, I should see my burst on the air at wall clock time? Can I assume t_analog is fixed for a given radio and can be found by calibration? Does this hold for N200? (I don’t see why it wouldn’t).
>  
> Extra beer at GRcon15 if there’s a similar formula for B210!
>  
> Sean
>  
> From: USRP-users [mailto:usrp-users-bounces at lists.ettus.com] On Behalf Of Ian Buckley via USRP-users
> Sent: Saturday, December 06, 2014 4:12 PM
> To: usrp-users at lists.ettus.com List
> Subject: Re: [USRP-users] N210 DSP Group delay
>  
> Oops typo in my own formula. Corrected version:
>  
> Input register: 1
> DC Offset Correction: 1
> IQ Balance: 2
> IQ Swap: 1
> CORDIC: 21
> Clip: 1
> CIC Filter: 5+6*DecCIC
> HB1: 7+6*DecCIC
> HB2: 9+8*(DecCIC*DecHB1*2)
> Clipping and Gain: 3
>  
> On Dec 5, 2014, at 4:13 PM, Ian Buckley <ianb at ionconcepts.com> wrote:
> 
> 
> Over the years a lot of people have asked for a figure for the group delay of N210.
> I finally had a reason to spend a few hours today putting together a formula to calculate the digital portion of it.
> 
> 
> Glossary:
> DecCIC - Decimation rate across the CIC filter
> DecHB1- Decimation rate across the small Half Band FIR (HB1)
> DecHB2 - Decimation rate across the large Half Band FIR (HB2)
> 
> For the N210 Rx path (Tx will be similar) ADC -> Packetization, sum the following:
> 
> Input register: 1
> DC Offset Correction: 1
> IQ Balance: 2
> IQ Swap: 1
> CORDIC: 21
> Clip: 1
> CIC Filter: 5+6*DecCIC
> HB1: 7+6*DecCIC
> HB2: 9+8*(DecCIC*DecHB1)
> Clipping and Gain: 3
> 
> This is the number of 100MHz (10nS) clock cycles used in the DSP pipeline before packets are timestamped and packetized.
> 
> For example if you had configured N210 to produce a 1MHz sample stream, thats Decimation=100 which maps to : 
> DecCIC=25, DecHB1=2, DecHB2=2. This makes group delay ~11.51uS
> 
> Another example. If you configured N210 to produce a 25<Hz sample stream, thats Decimation = 4 which maps to:
> DecCIC=1, DecHB1=2, DecHB2=2. This makes group delay ~790nS.
> 
> You can buy me a beer at GRC2015 to say thanks….(Note: if if there is an error in the formula, I won't be buying reciprocal beer!)
> -Ian
> 
>  

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