[USRP-users] N210 DSP Group delay

Perelman, Nathan nperelman at LGSInnovations.com
Mon Dec 8 12:29:18 EST 2014


Thanks, that's very informative. Is the DC Offset Correction part of the
delay present even if DC offset correction is disabled?

-Nathan

 

From: USRP-users [mailto:usrp-users-bounces at lists.ettus.com] On Behalf Of
Ian Buckley via USRP-users
Sent: Saturday, December 6, 2014 4:12 PM
To: usrp-users at lists.ettus.com List
Subject: Re: [USRP-users] N210 DSP Group delay

 

Oops typo in my own formula. Corrected version:

 

Input register: 1
DC Offset Correction: 1
IQ Balance: 2
IQ Swap: 1
CORDIC: 21
Clip: 1
CIC Filter: 5+6*DecCIC
HB1: 7+6*DecCIC
HB2: 9+8*(DecCIC*DecHB1*2)
Clipping and Gain: 3

 

On Dec 5, 2014, at 4:13 PM, Ian Buckley <ianb at ionconcepts.com> wrote:





Over the years a lot of people have asked for a figure for the group delay
of N210.
I finally had a reason to spend a few hours today putting together a formula
to calculate the digital portion of it.


Glossary:
DecCIC - Decimation rate across the CIC filter
DecHB1- Decimation rate across the small Half Band FIR (HB1)
DecHB2 - Decimation rate across the large Half Band FIR (HB2)

For the N210 Rx path (Tx will be similar) ADC -> Packetization, sum the
following:

Input register: 1
DC Offset Correction: 1
IQ Balance: 2
IQ Swap: 1
CORDIC: 21
Clip: 1
CIC Filter: 5+6*DecCIC
HB1: 7+6*DecCIC
HB2: 9+8*(DecCIC*DecHB1)
Clipping and Gain: 3

This is the number of 100MHz (10nS) clock cycles used in the DSP pipeline
before packets are timestamped and packetized.

For example if you had configured N210 to produce a 1MHz sample stream,
thats Decimation=100 which maps to : 
DecCIC=25, DecHB1=2, DecHB2=2. This makes group delay ~11.51uS

Another example. If you configured N210 to produce a 25<Hz sample stream,
thats Decimation = 4 which maps to:
DecCIC=1, DecHB1=2, DecHB2=2. This makes group delay ~790nS.

You can buy me a beer at GRC2015 to say thanks..(Note: if if there is an
error in the formula, I won't be buying reciprocal beer!)
-Ian

 

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